参数资料
型号: SC4519HSETRT
厂商: Semtech
文件页数: 10/14页
文件大小: 0K
描述: IC REG BUCK 3A 8-SOIC
标准包装: 1
类型: 降压(降压)
输出数: 1
输入电压: 4.4 V ~ 24 V
PWM 型: 电流模式
频率 - 开关: 600kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
包装: 标准包装
供应商设备封装: 8-SO 裸露焊盘
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC4519HSEDKR
SC4519H
POWER MANAGEMENT
Application Information (Cont.)
The junction temperature of the SC4519H can be
FB
further determined by:
T J = T A + θ JA ? P total
θ JA is the thermal resistance from junction to ambient.
Its value is a function of the IC package, the application
2
5
8
IN
EN
SYNC
SC4519H
3
SW
6
7
COMP
C4
L1
R1
R2
C
Vout
layout and the air cooling system.
C5
R3
D2
The freewheeling diode also contributes a significant
portion of the total converter loss. This loss should be
minimized to increase the converter efficiency by using
Schottky diodes with low forward drop (V F ).
P diode = V F ? I o ? (1 ? D)
Loop Compensation Design
Figure 3. Compensation network provides 2 poles and
1 zero.
The compensation network gives the following
characteristics:
1 +
s ? (1 +
The SC4519H has an internal error amplifier and requires
a compensation network to connect between the COMP
pin and GND pin as shown in Figure 3. The compensation
network includes C4, C5 and R3. R1 and R2 are used to
G COMP (s) = ω 1 ?
s
ω Z
s
ω P2
)
? g m ?
R 2
R 1 + R 2
program the output voltage according to:
Where:
V O = 0 . 8 ? ( 1 +
R 1
R 2
)
ω 1 =
1
C 4 + C 5
ω Z =
ω P2 =
Assuming the power stage ESR (equivalent series
resistance) zero is an order of magnitude higher than
the closed loop bandwidth, which is typically one tenth of
the switching frequency, the power stage control to output
transfer function with the current loop closed (Ridley
model) for the SC4519H will be as follows:
1
R 3 ? C 4
C 4 + C 5
R 3 ? C 4 ? C 5
1 +
1 +
T(s) = G COMP (s) ? G VD (s) = 4.25 ? 10 ? 3 ?
?
?
G VD (s) =
Where:
R L – Load and
C – Output capacitor.
5 ? R L
s
1
R L ? C
The loop gain will be given by:
s
R L R 2 1 ω Z
C 4 R 1 + R 2 s (1 + s ) ? (1 + s )
ω P1 ω P2
Where:
The goal of the compensation design is to shape the loop
to have a high DC gain, high bandwidth, enough phase
ω p1 =
1
R L ? C
margin, and high attenuation for high frequency noises.
Figure 3 gives a typical compensation network which
offers 2 poles and 1 zero to the power stage:
One integrator is added at origin to increase the DC gain.
ω Z is used to cancel the power stage pole ω P1 so that the
loop gain has –20dB/dec rate when it reaches 0dB line.
ω P2 is placed at half switching frequency to reject high
frequency switching noises. Figure 4 gives the asymptotic
diagrams of the power stage with current loop closed
and its loop gain.
? 2007 Semtech Corp.
10
www.semtech.com
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