参数资料
| 型号： | SC493ULTRT |
| 厂商： | Semtech |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM MLPQ-20 |
| 标准包装： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 3 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-MLPQ |
| 包装： | 标准包装 |
| 其它名称： | SC493ULTRTDKR |
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SC493
Applications Information (continued)
Ultrasonic Power-save
When ultrasonic PSAVE is enabled (PSV1,0 =10) the
minimum operating frequency in power save for the
SC493 is set by UPSV1,0 bits . This is accomplished by
using a built-in timer that detects the time between con-
secutive high-side gate pulses.
As soon as the time exceeds the the programmed upper
limit, the bottom gate is turned on. This prevents the con-
troller from going below the set limit in frequency when
the power save is enabled. Figure 2 shows ultrasonic
power-save operation.
Minimum F SW ~ 20kHz
UVLO and POR
Under-Voltage Lockout (UVLO) circuitry inhibits switching
and tri-states the output until VDD rises above 2.8V. An
internal Power-On Reset (POR) occurs until VDD exceeds
2.8V, which resets the internal registers, enables the I 2 C
interface, and resets the soft-start circuitry.
Smart Power-save Protection
Active loads may leak current from a higher voltage into
the switcher output. Under light load conditions with
power-save enabled, this can force V OUT to slowly rise and
reach the over-voltage threshold. Smart power-save pre-
vents this condition. When the FB voltage exceeds 10%
above nominal (exceeds 550mV), the device immediately
disables power-save, and DL drives high to turn on the
FB Ripple
Voltage (V FB )
Inductor
Current
DH
DL
On-time
(T ON )
40μsec time-out
FB threshold
(500mV)
(0A)
DH On-Time is triggered when
V FB reaches the FB Threshold
low-side MOSFET. This draws current from V OUT through
the inductor and causes V OUT to fall. When V FB drops back
to the 500mV trip point, a normal T ON switching cycle
begins. This method prevents an OVP fault and also cycles
energy from V OUT back to V IN . The device will return to
power-save operation on the next switching cycle if the
load remains light. Smart Power-Save allows the user to
minimize operating power by allowing the use of power
save mode in load conditions that would normally require
the use of forced continuous conduction mode. Figure 3
shows typical waveforms for the Smart Power-save
feature.
After the 40μsec time-out, DL drives high if V FB
has not reached the FB threshold.
Figure 2 — Ultrasonic Power-save (UPSV 1,0 = 11)
Power Good Output
The Power Good (PGD) output is an open-drain output
which requires a pull-up resistor. When the FB voltage falls
lower than 80% (typical) of the nominal voltage, PGD is
pulled low. It is held low until the FB voltage rises above
90% (typical) of the nominal voltage. PGD is held low
during start-up and will not be allowed to transition high
until soft-start is completed. PGD also transitions low if the
FB voltage rises above 120% (typical) of the nominal
voltage, it is held low until the FB voltage drops below 110%
V OUT drifts up to due to leakage
current flowing into C OUT
Smart Power Save
Threshold (550mV)
FB
threshold
DH and DL off
High-side
Drive (DH)
Single DH on-time pulse
after DL turn-off
Low-side
Drive (DL)
DL turns on when Smart
PSAVE threshold is reached
DL turns off when FB
threshold is reached
V OUT discharges via inductor
and low-side MOSFET
Normal V OUT ripple
Normal DL pulse after DH
on-time pulse
(typical) of the nominal voltage.
Figure 3 — Smart Power-save
15
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