参数资料
| 型号： | SC493ULTRT |
| 厂商： | Semtech |
| 文件页数： | 24/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM MLPQ-20 |
| 标准包装： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 3 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-MLPQ |
| 包装： | 标准包装 |
| 其它名称： | SC493ULTRTDKR |
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SC493
Serial Interface
The SC493 is a read-write slave-mode I C device and com-
TheI 2 CGeneralSpecification
2
plies with the Philips I 2 C standard Version 2.1, dated
January 2000. The SC493 has six user-accessible internal
8-bit registers. The I 2 C interface has been designed for
program flexibility, supporting direct format for write
operation. Read operations are supported on both com-
bined format and stop separated format. While there is
no auto increment/decrement capability in the SC493 I 2 C
logic, a tight software loop can be designed to randomly
access the next register independent of which register
was accessed first. The start and stop commands frame
the data-packet and the repeat start condition is allowed
if necessary.
SC493 Limitations to the I 2 C Specifications
The SC493 only recognizes seven bit addressing. This
means that ten bit addressing and CBUS communication
are not compatible. The device can operate in either stan-
dard mode (100kbit/s) or fast mode (400kbit/s).
Slave Address Assignment
The seven bit slave address is 0001A 2 A 1 A 0 x, where A 2 A 1 A 0
are set by the respective pins on the device. Bit 8 is the
data direction bit: 0001A 2 A 1 A 0 0 is used for a write opera-
tion, and 0001A 2 A 1 A 0 1 is used for a read operation.
Supported Formats
The supported formats are described in the following
subsections.
Direct Format — Write
address. The slave acknowledges and the master sends
the appropriate 8 bit data byte. Once again the slave
acknowledges and the master terminates the transfer with
the stop condition [P].
Combined Format — Read
After the start condition [S], the slave address is sent, fol-
lowed by an eighth bit indicating a write. The I 2 C logic
then acknowledges that it is being addressed, and the
master responds with an 8 bit data byte consisting of the
register address. The slave acknowledges and the master
sends the repeated start condition [Sr]. Once again, the
slave address is sent, followed by an eighth bit indicating
a read. The slave responds with an acknowledge and the
previously addressed 8 bit data byte; the master then
sends a non-acknowledge (NACK). Finally, the master ter-
minates the transfer with the stop condition [P].
Stop Separated Reads
Stop-separated reads can also be used. This format allows
a master to set up the register address pointer for a read
and return to that slave at a later time to read the data. In
this format the slave address followed by a write command
are sent after a start [S] condition. The SC493 then
acknowledges it is being addressed, and the master
responds with the 8-bit register address. The master sends
a stop or restart condition and may then address another
slave. After performing other tasks, the master can send a
start or restart condition to the SC493 with a read
command. The device acknowledges this request and
returns the data from the register location that had previ-
ously been set up.
The simplest format for an I 2 C write is direct format. After
the start condition [S], the slave address is sent, followed
by an eighth bit indicating a write. The I 2 C logic then
acknowledges that it is being addressed, and the master
responds with an 8 bit data byte consisting of the register
24
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