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参数资料
| 型号： | SC668ULTRT |
| 厂商： | Semtech |
| 文件页数： | 40/46页 |
| 文件大小： | 0K |
| 描述： | IC LED DRVR LMU 8CH MLPQUT20 |
| 特色产品： | Semtech sc667 and sc668 |
| 标准包装： | 1 |
| 拓扑： | 线性（LDO），PWM |
| 输出数： | 12 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，LED 闪烁器，照明管理装置（LMU） |
| 频率： | 400kHz |
| 电源电压： | 2.9 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-UFQFN 裸露焊盘 |
| 供应商设备封装： | 20-MLPQ（3x3） |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 其它名称： | SC668ULDKR |
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SC668
Register Map (continued)
ADC Function Register (12h)
This register is used to enable the functions of the ADC
and store related status bits. The ADC converts the analog
output voltage signal of an ALS (Ambient Light Sense)
circuit and stores the digital conversion in the ADC output
AD OUT (register 13h). The data may be used to automati-
cally adjust the brightness of bank #1 backlights in
response to changes in ambient lighting conditions.
AD_CMP [D7]
This bit indicates the comparison of AD OUT (register 13h) to
both AD RISE (register 14h) and AD FALL (register 15h). When
AD OUT exceeds AD RISE , AD_CMP = 1. When AD OUT falls below
AD FALL , AD_CMP = 0.
AD_INT [D6]
This bit is set when the AD_CMP bit [D7] changes state. If
the AD_SATEN [D5] bit is set, AD_INT bit [D6] may also be
used to indicate an overflow or underflow in AD OUT (register
13h). This bit is cleared when ADC function register (12h) is
read, or when writing INT_CLR bit [D2] equal to one.
The AD_INT bit provides a flag indicating that the ADI
input has exceeded a threshold level, or indicates that an
overflow or underflow condition exists. Figure 28 shows
the AD_INT flag interrupt states.
Interrupt is set
AD_INT ? 1
AD_SATEN [D5]
This bit, when set, allows an underflow or overflow to gen-
erate an interrupt which sets the AD_INT bit [D6]. When
AD_SATEN = 1, an overflow or underflow condition in reg-
ister 13h will set the AD_INT bit.
AD_OF [D4]
This bit indicates an overflow condition in register 13h. This
bit is set to one whenever AD OUT becomes AD OUT > F8h.
AD_UF [D3]
This bit indicates an underflow condition in register 13h. This
bit is set to one whenever AD OUT becomes AD OUT < 08h.
INT_CLR [D2]
Writing a one to this bit automatically resets bit AD_INT to
zero. INT_CLR resets itself and will always read as zero.
AD_AUTO [D1]
When the AD_AUTO bit is high, the contents of the AD OUT ,
AD RISE , and AD FALL registers are compared and used to control
the brightness of backlight bank #1. AD OUT is compared with
two threshold values contained in registers AD RISE and
AD FALL . If AD OUT becomes greater than AD RISE , bank #1 will
change to the bank #1 target backlight setting of register
06h. If AD OUT becomes less than AD FALL , bank #1 will change
to the bank #1 backlight setting from register 02h.
When the AD_AUTO bit is low, the comparison of AD OUT to
AD RISE and AD FALL is disabled so that bank #1 does not react
to changes in the value of AD OUT , AD RISE , or AD FALL .
AD_EN [D0]
When the AD_EN bit is high, the ADC is activated and the
Bit
AD_CMP
changes
state
AD_OF = 1
or
AD_UF = 1
and
AD_SAT
0 ? 1
AD_SAT = 1
and
AD_OF
0 ? 1
or
AD_UF
0 ? 1
AD_SAT = 0
Read
register 12h
or
Write
CLR_INT = 1
results of each conversion are stored in AD OUT (register 13h).
The functions of the AD_AUTO and AD_EN bits are shown
in Table 22.
Interrupt is reset
AD_INT ? 0
Figure 28 — ADC Interrupt State Diagram
40
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