参数资料
型号: SCAN182245ASSC
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 总线收发器
中文描述: SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PDSO56
封装: 0.300 INCH, MO-118, SSOP-56
文件页数: 6/13页
文件大小: 133K
代理商: SCAN182245ASSC
www.fairchildsemi.com
2
SCAN18224
5A
Truth Tables
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
Note 1: Inactive-to-Active transition must occur to enable outputs upon power-up.
Functional Description
The SCAN182245A consists of two sets of nine non-invert-
ing bidirectional buffers with 3-STATE outputs and is
intended for bus-oriented applications. Direction pins (DIR1
and DIR2) LOW enables data from B Ports to A Ports,
when HIGH enables data from A Ports to B Ports. The Out-
put Enable pins (G1 and G2) when HIGH disables both A
and B Ports by placing them in a high impedance condition.
Block Diagrams
A1, B1, G1 and DIR1
Note: BSR stands for Boundary Scan Register.
A2, B2, G2 and DIR2
Note: BSR stands for Boundary Scan Register.
Tap Controller
Inputs
A1(0–8)
B1(0–8)
G1
(Note 1)
DIR1
LL
H
H
LL
L
L
LH
H
H
LH
L
L
HX
Z
Inputs
A2(0–8)
B2(0–8)
G2
(Note 1)
DIR2
LL
H
H
LL
L
L
LH
H
H
LH
L
L
HX
Z
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