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参数资料
| 型号： | SCC2698BE1A84,518 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 5/29页 |
| 文件大小： | 0K |
| 描述： | IC UART OCTAL ENHANCED 84-PLCC |
| 标准包装： | 250 |
| 特点： | 故障启动位检测 |
| 通道数： | 8 |
| FIFO's： | 3 位 |
| 电源电压： | 5V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 84-LCC（J 形引线） |
| 供应商设备封装： | 84-PLCC |
| 包装： | 带卷 (TR) |
| 其它名称： | 935056380518 SCC2698BE1A84-T SCC2698BE1A84-T-ND |
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Philips Semiconductors
Product data sheet
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2006 Aug 07
13
Table 2. Register Bit Formats
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MR1 (Mode Register 1)
RxRTS
Control
RxINT Select
Error Mode*
Parity Mode
Parity Type
Bits per Character
0 = No
0 = RxRDY
0 = Char
00 = With parity
0 = Even
00 = 5
1 = Yes
1 = FFULL
1 = Block
01 = Force parity
1 = Odd
01 = 6
10 = No parity
10 = 7
11 = Special mode
11 = 8
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2)
Channel Mode
TxRTS
Control
CTS Enable
Tx
Stop Bit Length*
00 = Normal
0 = 0.563
4 = 0.813
8 = 1.563
C = 1.813
01 = Auto-echo
0 = No
1 = 0.625
5 = 0.875
9 = 1.625
C = 1.875
10 = Local loop
1 = Yes
2 = 0.688
6 = 0.938
A = 1.688
E = 1.938
11 = Remote loop
3 = 0.750
7 = 1.000
B = 1.750
F = 2.000
NOTE: *Add 0.5 to values shown above for 0–7, if channel is programmed for 5 bits/char.
CR (Command Register)
Miscellaneous Commands
Disable Tx
Enable Tx
Disable Rx
Enable Rx
See text
0 = No
See text
1 = Yes
NOTE: Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter
cannot be loaded
SR (Status Register)
Rec’d Break*
Framing
Error*
Parity Error*
Overrun Error
TxEMT
TxRDY
FFULL
RxRDY
0 = No
1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these
bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command. In character mode, they
must be reset when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by
using the error reset command (command 4x) or a receiver reset.
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