参数资料
型号: SCDV5540
厂商: SIEMENS A G
元件分类: 显示用LED
英文描述: 5X5 DOT MATRIX DISPLAY, RED, 3.2 mm
封装: PLASTIC, DIP-14
文件页数: 10/14页
文件大小: 180K
代理商: SCDV5540
5
SCDV5540/1/2/3/4
Pin assignment
Switching specications
(over operating temperature range and VCC=4.5 V to 5.5 V)
Note:
TSDCW is the minimum time the SDCLK may be low or high.
The SDCLK period must be a minimum of 200 ns.
Figure 6. Dot matrix format
Pin
Function
Pin
Function
1
SDCLK
14
GND
2
LOAD
13
DATA
3NP
12
VCC
4NP
11
VCC
5NP
10
VCC
6
RST
9
CLKSEL
7
GND
8
CLK I/O
Symbol
Description
Min.
Units
TRC
Reset Active Time
600
ns
TLDS
Load Setup Time
50
ns
TDS
Data Setup Time
50
ns
TSDCLK
Clock Period
200
ns
TSDCW
Clock Width
70
ns
TLDH
Load Hold Time
0
ns
TDH
Data Hold Time
25
ns
TWR
Total Write Time
2.2
s
TBL
Time Between Loads
600
ns
0.095
(2.41)
0.123 (3.12)
0.021 (0.53)
0.028 (0.71)
Dimensions in inches (mm)
Tolerance: .XXX=
±.010 (.25)
Pin denitions
Display column and row format
Column data ranges
Pin
Function
Denitions
1
SDCLK
Loads data into the 8-bit serial
data register on a low to high
transition.
2
LOAD
Low input enables data clocking
into 8-bit serial shift register.
When LOAD goes high, the con-
tents of 8-bit serial Shift Register
will be decoded.
3
NP
No pin
4
NP
No pin
5
NP
No pin
6
RST
Asynchronous input, when low
will clear the Multiplex Counter,
User RAM and Data Register.
Control Word Register is set to
100% brightness and the Address
Register is set to select Digit 0.
The display is blanked.
7
GND
Power supply ground
8
CLK I/O
Outputs master clock or inputs
external clock.
9
CLK SEL
H=internal clock, L=external clock
10
VCC
Power supply
11
VCC
Power supply
12
VCC
Power supply
13
DATA
Serial data input
14
GND
Power supply ground
C0
C1
C2
C3
C4
Row 0
11111
Row 1
00100
Row 2
00100
Row 3
00100
Row 4
00100
Row 0
00H to 1FH
Row 1
20H to 3FH
Row 2
40H to 5FH
Row 3
60H to 7FH
Row 4
80H to 9FH
1=Display dot “On”
0=Display dot “Off’
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