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参数资料
| 型号： | SCDV5540 |
| 厂商： | SIEMENS A G |
| 元件分类： | 显示用LED |
| 英文描述： | 5X5 DOT MATRIX DISPLAY, RED, 3.2 mm |
| 封装： | PLASTIC, DIP-14 |
| 文件页数： | 12/14页 |
| 文件大小： | 180K |
| 代理商： | SCDV5540 |
7
SCDV5540/1/2/3/4
The following explains how to format the serial data to be
loaded into the display. The user supplies a string of bit mapped
decoded characters. The contents of this string is shown in Fig-
ure 8a. Figure 8b shows that each character consists of six 8 bit
words. The rst word encodes the display character location
and the succeeding ve bytes are row data. The row data repre-
sents the status (On, Off) of individual column LEDs. Figure 8c
shows that each that each 8 bit word is formatted to include a
three bit Operational Code (OPCODE) dened by bits D7–D5
and ve bits (D4–D0) representing Column Data, Character
Address, or Control Word Data.
Figure 8d shows the sequence for loading the bytes of data.
Bringing the LOAD line low enables the serial register to accept
data. The shift action occurs on the low to high transition of the
serial data clock (SDCLK). The least signicant bit (D0) is loaded
rst. After eight clock pulses the LOAD line is brought high.
With this transition the OPCODE is decoded. The decoded
OPCODE directs D4–D0 to be latched in the Character Address
register, stored in the RAM as Column data, or latched in the
Control Word register. The control IC requires a minimum 600
ns delay between successive byte loads. As indicated in Figure
8a, a total of 264 bits of data are required to load all eight char-
acters into the display.
Figure 8. Loading serial character data
Character 0
Character 1
Character 2
Character 3
264 Clock Cycles, 52.8 s
Example: Serial Clock = 5MHz, Clock Period = 200ns
Time between LOADS
LOAD
Serial
Clock
DATA
Clock
Period
t 0
D0
D1
D2
D3
D4
D5
D6
D7
11 Clock Cycles, 2.2s
Time
Between
Loads
600ns(min)
OPCODE
Character Address
OPCODE
Column Data
D0
C4
D1
C3
D2
C2
D3
C1
D4
C0
Time
Between
Loads
600ns(min)
11 Clock Cycles, 2.2s
Character 0
Address
Row 0 Column
Data
66 Clock Cycles, 13.2s
Row 1 Column
Data
Row 2 Column
Data
Row 3 Column
Data
Row 4 Column
Data
D0
0
D1
0
D2
0
D3
0
D4
0
D5
1
D6
0
D7
0
D5
D6
D7
a.
b.
c.
d.
The Character Address Register bits, D4–D0 (Table 2), and Row
Address Register bits, D7–D5 (Table 3), direct the Column Data
bits, D4–D0 (Table 3) to specic RAM location. Table 1 shows
the Row Address for the example character “D.” Column data
is written and read asynchronously from the 200 bit RAM.
Once loaded the internal oscillator and character multiplexer
reads the data from the RAM. These characters are row
strobed with column data as shown in Figures 9 and 10. The
character strobe rate is determined by the internal or user sup-
plied external MUX Clock and the IC’s
÷ 320 counter.
Table 1. Character “D”
Op code
D7 D6 D5
Column Data
D4 D3 D2 D1 D0
C0 C1 C2 C3 C4
Hex
Row 0
0
1
0
1E
Row 1
0
1
0
1
31
Row 2
0
1
0
1
0
1
51
Row 3
0
1
0
1
71
Row 4
1
0
1
0
9E
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