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参数资料
| 型号： | SED1336F0A |
| 元件分类： | 显示控制器 |
| 英文描述： | 640 X 256 DOTS DOT MAT LCD DSPL CTLR, PQFP60 |
| 封装： | PLASTIC, QFP6-60 |
| 文件页数： | 12/12页 |
| 文件大小： | 50K |
| 代理商： | SED1336F0A |
161
° Display Memory Write Timing
Signal
Symbol
Parameter
VDD = 4.5 to 5.5V
VDD = 3.0 to 4.5V
Unit
Condition
min
max
min
max
EXT
φ0tC
Clock period
100
—
125
—
ns
tW
VCE HIGH-level pulse-
tC – 50
—
tC – 50
—
ns
VCE
width
tCE
VCE LOW-level pulse-
2tC – 30
—
2tC – 30
—
ns
width
tCYW
Write cycle time
3tC
—3tC
—ns
tAHC
Address hold time from
2tC – 30
—
2tC – 40
—
ns
falling edge of VCE
tASC
Address setup time to
tC – 70
—
tC – 100
—
ns
falling edge of VCE
VA0 to
tCA
Address hold time from
0—
ns
VA15
rising edge of VCE
tAS
Address setup time to
0—
ns
falling edge of VWR
tAH2
Address hold time from
10
—
10
—
ns
rising edge of VWR
tWSC
Write setup time to
tC – 80
—
tC – 110
—
ns
VWR
falling edge of VCE
tWHC
Write hold time from
2tC – 20
—
2tC – 20
—
ns
falling edge of VCE
tDSC
Data input setup time
tC – 85
—
tC – 120
—
ns
to falling edge of VCE
VD0 to
tDHC
Data input hold time
2tC – 30
—
2tC – 30
—
ns
VD7
from falling edge of VCE
tDH2
Data hold time from
550
5
50
ns
rising edge of VWR
Ta = –20 to 75
°C
CL =
100 pF
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
EXT
φ0
VCE
VA0 to VA15
VRW
VD0 to VD7
tC
tW
tCE
tCA
tAHC
tASC
tCYW
tAS
tDSC
tDHC
tAH2
tDH2
tWSC
tWHC
SED1336
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SED1351 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GRAPHICS LCD CONTROLLER |
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| SED1351F0A | 制造商:Seiko Instruments Inc (SII) 功能描述: |
| SED1352 | 制造商:EPSON 制造商全称:EPSON 功能描述:Document Number: X16B-Q-001-06 |
| SED1353 | 制造商:EPSON 制造商全称:EPSON 功能描述:SED1353 GRAPHICS LCD CONTROLLER |
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