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参数资料
| 型号： | SEN01G64D1BF1SA-30WR |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | DRAM DDR2 1GB 200-SODIMM |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 100 |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 1GB |
| 速度： | 667MHz |
| 封装/外壳： | 200-SODIMM |
| 其它名称： | 1052-1041 |
Data Sheet
I DD Specifications and Conditions
(0°C ≤ T CASE ≤ + 85°C ; V DDQ = +1.8V ± 0.1V, V DD = +1.8V ± 0.1V)
Rev.1.2
09.11.2010
Parameter
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
Symbol
I DD0
max
5300-555
344
6400-666
360
Unit
mA
t RC = t RC (I DD ); t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
I DD1
384
408
mA
I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0;
t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ),
t RCD = t RCD (I DD ); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as I DD4W
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
I DD2P
80
80
mA
t CK = t CK (I DD ); CKE is LOW; All Control and Address
bus inputs are not changing; DQ’s are floating at V REF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
I DD2Q
160
160
mA
t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at V REF
PRECHARGE STANDBY CURRENT:
All device banks idle;
I DD2N
192
200
mA
t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN
CURRENT:
All device banks open; t CK = t CK
(I DD ); CKE is LOW; All Control and
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
I DD3P
184
120
176
120
mA
Address bus inputs are not
changing; DQ’s are floating at V REF
ACTIVE STANDBY CURRENT:
All device banks open; t CK = t CK (I DD ),
I DD3N
240
256
mA
t RAS = t RAS MAX (I DD ), t RP = t RP (I DD );
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
All device banks open, Continuous burst reads; One
I DD4R
560
640
mA
module rank active; I OUT = 0mA; BL = 4, CL = CL (I DD ),
AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP
(I DD ); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
Swissbit AG
Industriestrasse 4
Ch-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 7
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