参数资料
型号: SGN08G64B3BB2SA-CCWRT
厂商: Swissbit NA Inc
文件页数: 2/15页
文件大小: 0K
描述: SDRAM DDR3 8GB 204 SO-DIMM
特色产品: 64-Bit DDR3 SDRAM Module
标准包装: 1
存储器类型: DDR3 SDRAM
存储容量: 8GB
速度: 1333MT/s
封装/外壳: 204-SODIMM
其它名称: 1052-1067
preliminary Data Sheet
Rev.0.9
15.11.2011
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM Small Outline Dual-In-line Memory
Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally
configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-
speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power- saving “power - down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
utilized by the SO- DIMM manufacturer (Swissbit) to identify the module type, the module’s or ganization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
1G x 64bit
DDR3 SDRAMs used
16 x 512M x 8bit (4096Mbit)
Row
Addr.
16
Device Bank
Addr.
BA0, BA1, BA2
Column
Addr.
10
Refresh
8k
Module
Bank Select
S0#, S1#
Module Dimensions
in mm
67.60 (long) x 30(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
SGN08G64B3BB2SA-CCRT
SGN08G64B3BB2SA-DCRT
Module Density
8192MB
8192MB
Data Rate
10.6 GB/s
12.8 GB/s
Clock Cycle/Data bit rate
1.50ns / 1333MT/s
1.25ns / 1600MT/s
Latency
9-9-9
11-11-11
Pin Name
A0-9, A11 – A15
A10/AP
A12/BC#
BA0 – BA2
DQ0 – DQ63
DM0-DM7
DQS0 - DQS7
DQS0# - DQS7#
S0#, S1#
RAS#
CAS#
WE#
CKE0, CKE1
ODT0, ODT1
CK0, CK1
Swissbit AG
Address Inputs
Address Input / Autoprecharge Bit
BC switch on the fly
Bank Address Inputs
Data Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
On-Die Termination
Clock Inputs, positive line
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
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