参数资料
型号: SI3018-F-FS
厂商: Silicon Laboratories Inc
文件页数: 62/94页
文件大小: 0K
描述: IC ISOMODEM LINE-SIDE DAA 16SOIC
标准包装: 48
系列: ISOmodem®
数据格式: V.92
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC N
包装: 管件
Si3056
Si3018/19/10
Rev. 1.05
65
Reset settings = 1001_0110
Register 22. Ring Validation Control 1
Bit
D7D6D5
D4
D3D2
D1
D0
Name
RDLY[1:0]
RMX[5:0]
Type
R/W
Bit
Name
Function
7:6
RDLY[1:0]
Ring Delay Bits 1 and 0.
These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
RDLY[1:0]
Delay
000
0 ms
001
256 ms
010
512 ms
.
1
11
1792 ms
5:0
RMX[5:0]
Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal within a 10% margin of
error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING
event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the
timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then
the frequency of the ring is too high and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/
(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,
f_max], the following equation should be used:
To compensate for error margin and ensure a sufficient ring detection window, it is recom-
mended that the calculated value of RMX[5:0] be incremented by 1.
RMX 5:0
[] RAS 5:0
[]
1
2 f_max
×
2 ms
×
--------------------------------------------- RMX RAS
,
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