参数资料
型号: SI3452C-B01-GM
厂商: Silicon Laboratories Inc
文件页数: 26/36页
文件大小: 0K
描述: IC POE CONTROLLER MIDSPAN 40QFN
特色产品: Si3452 Quad High-Voltage Port Controller for PoE and PoE+PSEs
标准包装: 50
控制器类型: 以太网供电控制器(POE)
接口: I²C
电源电压: 3 V ~ 3.6 V
电流 - 电源: 14mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
配用: SMARTPSE24-KIT-ND - KIT EVAL REF 24PORT SPI/UART
SI3480MS8-KIT-ND - KIT EVAL 8PORT SI3480/52/SI3500
其它名称: 336-1834-5
Si3452
32
Rev. 1.3
11. Recommended PCB Footprint
Figure 8. PCB Land Pattern
Table 27. PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
5.80
5.90
X2
4.10
4.20
C2
5.80
5.90
Y1
0.75
0.85
e
0.50 BSC
Y2
4.10
4.20
X1
0.15
0.25
Notes:
General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4.
All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5.
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60
m minimum, all the way around the pad.
Stencil Design
6.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
7.
The stencil thickness should be 0.125 mm (5 mils).
8.
The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9.
A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground pad.
Card Assembly
10.
A No-Clean, Type-3 solder paste is recommended.
11.
Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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