参数资料
型号: SI4021-A1-FT
厂商: Silicon Laboratories Inc
文件页数: 12/34页
文件大小: 783K
描述: IC TX FSK 915MHZ 5.4V 16-TSSOP
标准包装: 96
频率: 433MHz,868MHz,915MHz
调制或协议: FSK,OOK
数据传输率 - 最大: 512kbps
功率 - 输出: 8dBm
电流 - 传输: 24mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 2.2 V ~ 5.4 V
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 585 (CN2011-ZH PDF)
其它名称: 336-1622-5
Si4021
 
 
12
CONTROL INTERFACE
Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK
whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent is an integer
multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first
(e.g. bit 15 for a 16-bit command). Bits having no influence (dont care) are indicated with X. The Power On Reset (POR) circuit sets default
values in all control and command registers.
The status information or received data can be read serially over the IRQ pin. Bits are shifted out upon the falling edge of CLK signal
Timing Specification
Symbol
Parameter
Minimum value [ns]
t
CH
 
Clock high time
25
t
CL
 
Clock low time
25
t
SS
 
Select setup time (nSEL falling edge to SCK rising edge)
10
t
SH
 
Select hold time (SCK falling edge to nSEL rising edge)
10
t
SHI
 
Select high time
25
t
DS
 
Data setup time (SDI transition to SCK rising edge)
5
t
DH
 
Data hold time (SCK rising edge to SDI transition)
5
t
OD
 
Data delay time
10
t
BL
 
Push-button input low time
25
 
Timing Diagram
SCK
SDI
nIRQ
nSEL
t
DS
t
DH
t
CH
t
CL
BIT15
BIT14
BIT13
t
SS
POR
BIT8
BIT7
t
OD
WK-UP
nIRQ
BIT1
BIT0
t
SH
t
SHI
 
 
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