参数资料
型号: SI4021-A1-FT
厂商: Silicon Laboratories Inc
文件页数: 26/34页
文件大小: 783K
描述: IC TX FSK 915MHZ 5.4V 16-TSSOP
标准包装: 96
频率: 433MHz,868MHz,915MHz
调制或协议: FSK,OOK
数据传输率 - 最大: 512kbps
功率 - 输出: 8dBm
电流 - 传输: 24mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 2.2 V ~ 5.4 V
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 585 (CN2011-ZH PDF)
其它名称: 336-1622-5
Si4021
 
 
26
Sensitive Reset Enabled, Ripple on V
dd
:
time
V
dd
Reset threshold voltage
(600mV)
nRes
output
H
L
1.6V
Reset ramp line
(100mV/ms)
 
Sensitive reset disabled:
time
V
dd
Reset threshold voltage
(600mV)
nRes
output
H
L
250mV
Reset ramp line
(100mV/ms)
 
Software reset
Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The result of the
command is the same as if power-on reset was occurred.
Vdd line filtering
During the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to keep
the Vdd line as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out
from reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing signal below
10mVp-p in the DC  50kHz range for 200ms from Vdd ramp start.. Typical example when a switch-mode regulator is used to supply the radio,
switching noise may be present on the Vdd line. Follow the manufacturers recommendations how to decrease the ripple of the regulator IC
and/or how to shift the switching frequency.
Related control commands
PLL setting and Reset Mode Command
Setting bit<1> to high will change the reset mode to normal from the default sensitive.
SW Reset Command
Issuing FE00h command will trigger software reset. See the Wake-up Timer Command.
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