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参数资料
| 型号： | SI4322-A0-FT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC RX FSK UNI 868/915MHZ 16TSSOP |
| 标准包装： | 96 |
| 频率： | 868MHz，915MHz |
| 灵敏度： | -104dBm |
| 数据传输率 - 最大： | 256 kbps |
| 调制或协议： | FSK |
| 应用： | 遥控，RKE，安全系统 |
| 电流 - 接收： | 14mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 特点： | 配有 RSSI |
| 电源电压： | 2.2 V ~ 3.8 V |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
Si4322
Status Read Command
The read command starts with a zero, whereas all other control commands start with a one. Therefore, after receiving the first bit of
the control command the Si4322 identifies it as a read command. So as the first bit of the command is received, the receiver starts
to clock out the status bits on the SDO output as follows:
Status Register Read Sequence with FIFO Read Example
nSEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
instruction
SDI
interrupt bits
demodulator status bits
AFC status bits
SDO
FIFO IT
FFOV*
WK-UP*
LBD*
FFEM
DRSSI
DQD
CRL
ATGL
ASAME
OFFS<6> OFFS<4> OFFS<3> OFFS<2> OFFS<1> OFFS<0>
FIFO IT
(SIGN)
*NOTE: Marked bits are internally latched.
Others are multiplexed out only.
Not e :
The FIFO IT bit behaves like a status bit, but generates nIRQ pulse if active. To check whether there is a sufficient amount of data
in the FIFO, the SDO output can be tested. In extreme speed critical applications, it can be useful to read only the first four bits
( FIFO IT - LBD ) to clear the FFOV, WK-UP, and LBD bits. During the FIFO access the f SCK cannot be higher than f ref /4, where f ref is the
crystal oscillator frequency. If the FIFO is read in this mode the nFFS input must be connected to logic high level.
Definitions of the bits in the above timing diagram:
FFIT
FFOV
WK-UP
LBD
FFEM
DRSSI
DQD
CRL
ATGL
ASAME
OFFS(6)
OFFS(4) -OFFS(0)
The number of data bits in the FIFO has reached the preprogrammed limit
FIFO overflow
Wake-up timer overflow
Low battery detect, the power supply voltage is below the preprogrammed limit
FIFO is empty
The strength of the incoming signal is above the preprogrammed limit
Data Quality Detector detected a good quality signal
Clock recovery lock
Toggling in each AFC cycle
AFC measured twice the same result
MSB of the measured frequency offset (sign of the offset value)
Offset value to be added to the value of the selected center frequency
16
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