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| 型号： | SI4770-A20-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 31/54页 |
| 文件大小： | 0K |
| 描述： | IC RECEIVER AM/FM CE HP |
| 特色产品： | Si477x Pro-Audio, High-Performance AM/FM Receiver and HD Radio Tuner |
| 标准包装： | 490 |
| 频率： | 520kHz ~ 1.71MHz，64MHz ~ 108MHz |
| 调制或协议： | AM，FM，RDS |
| 应用： | 通用 |
| 电流 - 接收： | 140mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 特点： | 配有 RSSI |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
| 配用： | 336-2267-ND - EVAL MODULE AM/FM CE SI4770 336-2269-ND - BOARD EVAL FOR CE AM/FM SI4770 |
| 其它名称： | 336-2268 SI4770-A10-GM SI4770-A10-GM-ND |
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Si4770/77-A20
4.8. Channel Equalizer
The Si4770/77-A20 supports advanced FM multi-path
channel equalization. Multi-path interference results in
fading of the FM signal at the receiver. Frequency
selective fading causes different frequencies of an input
signal to be attenuated and phase shifted differently in a
channel. Frequency selective fading gives rise to
notches in the frequency response of the channel. The
Si4770/77-A20 channel equalizer performs blind
equalization utilizing proprietary constant modulus
algorithm (CMA) to restore the flat response of the
channel.
4.9. Digital ZIF I/Q Interface
(Si4777 Only)
The digital ZIF I/Q output can provide the down
converted channelized AM/FM signal at baseband to a
third-party processor for AM/FM HD radio processor for
IBOC signal processing. The Si4777 provide a 500 kHz
BW signal for FM IBOC signal processing and a 30 kHz
BW signal for AM IBOC signal processing. The ZIF I/Q
4-pin interface consists of two data serial lines
containing I and Q data, a bit clock, and a word frame
for each data sample. The interface operates in master
mode and supports five different data formats:
? I 2 S ZIF
4.9.1. ZIF I/Q Data Formats
In I 2 S format, by default, the MSB is captured on the
second rising edge of IQCLK following each IQFS
transition. The remaining bits of the word are sent in
order, down to the LSB.
In Left-Justified format, by default, the MSB is captured
on the first rising edge of IQCLK following each IQFS
transition. The remaining bits of the word are sent in
order, down to the LSB.
In Right-Justified format, by default, the LSB is captured
on the last rising edge of IQCLK in each valid IQFS
interval.
In DSP format, the IQFS becomes a pulse with a width
of 1 IQCLK period. There are two options in transferring
the digital baseband I/Q data in DSP format: the MSB of
I and Q data can be transferred on the first rising edge
of IQCLK following the IQFS pulse (left-justified DSP
format) or on the second rising edge.
In all data formats, depending on the word size, IQCLK
frequency, and sample rates, there may be unused
IQCLK cycles after the LSB of each word before the
next IQFS transition and MSB of the next word. In
addition, if preferred, the user can configure the MSB to
be captured on the falling edge of IQCLK via properties.
The number of baseband I/Q bits is configured for 16
bits.
?
?
?
?
Left-Justified ZIF
Right-Justified ZIF
DSP ZIF
DSP Left-Justified ZIF
Table 14. ZIF I/Q Interface Description
Pin
IOUT
QOUT
IQFS
IQCLK
Description
16-bit baseband I word
16-bit baseband Q word
Word frame sync for I and Q words
Bit clock for I and Q data
Rev. 0.9
31
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| Si4774DY-T1-GE3 | 功能描述:MOSFET 30 Volts 16 Amps 5 Watts RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
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