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| 型号： | SI5323-B-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 1/40页 |
| 文件大小： | 0K |
| 描述： | IC MULTIPLIER/ATTENUATOR 36QFN |
| 标准包装： | 50 |
| 系列： | DSPLL® |
| 类型： | 时钟乘法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 无/是 |
| 电源电压： | 1.71 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 管件 |
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Rev. 1.0 1/11
Copyright 2011 by Silicon Laboratories
Si5323
P IN-P ROGRAMMABLE P RECISION C LOCK
M ULTIPLIER/J ITTER A TTENUATOR
Features
Applications
Description
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed
communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to
1050 MHz. The input clock frequency and clock multiplication ratio are selectable
from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is
based on Silicon Laboratories' 3rd-generation DSPLL technology, which
provides any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V
supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in
high performance timing applications.
Functional Block Diagram
Pin-selectable output frequencies
ranging from 8 kHz–708 MHz
Ultra-low jitter clock outputs as low
as 250 fs rms (12 kHz–20 MHz)
270 fs rms (50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz–8.4 kHz)
Meets ITU-T G.8251 and Telcordia
OC-192 GR-253-CORE jitter
specifications
Hitless input clock switching with
phase build-out and digital hold
Dual clock outputs with selectable
signal format (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 FEC ratios
(255/238, 255/237, 255/236)
LOL, LOS alarm outputs
Pin-controlled output phase adjust
Single supply 1.8 ±5%, 2.5 or 3.3 V
±10% operation with high PSRR
On-chip voltage regulator
Small size: 6 x 6 mm 36-lead QFN
SONET/SDH OC-48/STM-16 and
OC-192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 line cards
Optical modules
Test and measurement
Synchronous Ethernet
DSPLL
Loss of Signal
Clock Select
Bandwidth Select
Frequency Select
Disable/BYPASS
Xtal or Refclock
Signal Format
CKOUT2
CKIN1
CKOUT1
CKIN2
Control
Manual/Auto Switch
/
Skew Control
Signal Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Loss of Lock
Rate Select
Ordering Information:
See page 33.
Pin Assignments
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
FRQTBL
AUTOSEL
RST
C2B
C1B
GND
VDD
XA
VDD
RATE0
CK
IN
2+
CK
IN
2–
D
B
L2
_BY
RATE1
CKIN1
+
CKIN1
–
CS_CA
BWSEL0
BWSEL1
FRQSEL1
FRQSEL2
FRQSEL3
CK
OU
T1
–
SFOUT1
GND
VDD
SF
O
U
T
0
CKOUT2
–
CKOUT2
+
NC
GND
Pad
FRQSEL0
INC
9
18
19
28
XB
LO
L
DEC
CKOU
T
1+
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5323-B-GMR | 制造商:Silicon Laboratories Inc 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATO - Tape and Reel |
| Si5323-C-GM | 功能描述:锁相环 - PLL PIN-PROGRAMMABLE CLK MULT / JITTER ATTEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| SI5323-C-GMR | 功能描述:时钟合成器/抖动清除器 Pin-Ctrl Clk Xplier Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| SI5323-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5324 | 制造商:SILABS 制造商全称:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
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