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| 型号： | SI5323-B-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 7/40页 |
| 文件大小： | 0K |
| 描述： | IC MULTIPLIER/ATTENUATOR 36QFN |
| 标准包装： | 50 |
| 系列： | DSPLL® |
| 类型： | 时钟乘法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 无/是 |
| 电源电压： | 1.71 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 管件 |
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Si5323
Rev. 1.0
15
3. Functional Description
The Si5323 is a jitter-attenuating precision clock
multiplier for high-speed communication systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5323 accepts dual clock inputs ranging
from 8 kHz to 707 MHz and generates two frequency-
multiplied clock outputs ranging from 8 kHz to
1050 MHz. The two input clocks are at the same
frequency and the two output clocks are at the same
frequency. The input clock frequency and clock
multiplication ratio are selectable from a table of popular
SONET, Ethernet, and Fibre Channel rates. In addition
to providing clock multiplication in SONET and datacom
applications, the Si5323 supports SONET-to-datacom
frequency translations. Silicon Laboratories offers a PC-
based software utility, DSPLLsim, that can be used to
look up valid Si5323 frequency translations. This utility
can be downloaded from http://www.silabs.com/timing
(click on Documentation).
The Si5323 is based on Silicon Laboratories' 3rd-
generation DSPLL technology, which provides any-
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5323
PLL loop bandwidth is selectable via the BWSEL[1:0]
pins and supports a range from 60 Hz to 8.4 kHz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5323 supports hitless switching between the two
input clocks in compliance with GR-253-CORE and GR-
1244-CORE that greatly minimizes the propagation of
phase transients to the clock outputs during an input
clock transition (<200 ps typ). Manual and automatic
revertive and non-revertive input clock switching options
are available via the AUTOSEL input pin. The Si5323
monitors both input clocks for loss-of-signal and
provides a LOS alarm when it detects missing pulses on
either input clock. The device monitors the lock status of
the PLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock.
The Si5323 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL generates an output frequency
based on a historical average that existed a fixed
amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
The Si5323 has two differential clock outputs. The
electrical format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, the second clock output can be powered down
to minimize power consumption. The phase difference
between the selected input clock and the output clocks
is adjustable in 200 ps increments for system skew
control. For system-level debugging, a bypass mode is
available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
3.1. External Reference
An
external,
38.88 MHz
clock
or
a
low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high-quality crystal. Specific recommendations
may be found in the Any-Frequency Precision Clock
Family Reference Manual. An external clock from a high
quality OCXO or TCXO can also be used as a reference
for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
3.2. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5323. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing (click on
Documentation).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5323-B-GMR | 制造商:Silicon Laboratories Inc 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATO - Tape and Reel |
| Si5323-C-GM | 功能描述:锁相环 - PLL PIN-PROGRAMMABLE CLK MULT / JITTER ATTEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| SI5323-C-GMR | 功能描述:时钟合成器/抖动清除器 Pin-Ctrl Clk Xplier Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| SI5323-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5324 | 制造商:SILABS 制造商全称:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
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