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| 型号： | SI5323-B-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 24/40页 |
| 文件大小： | 0K |
| 描述： | IC MULTIPLIER/ATTENUATOR 36QFN |
| 标准包装： | 50 |
| 系列： | DSPLL® |
| 类型： | 时钟乘法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 无/是 |
| 电源电压： | 1.71 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 管件 |
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Si5323
30
Rev. 1.0
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock
indicator.
0 = PLL locked
1 = PLL unlocked
19
DEC
I
LVCMOS
Skew Decrement.
A pulse on this pin decreases the input to output device skew
by 1/fOSC (approximately 200 ps). There is no limit on the
range of skew adjustment by this method. If both INC and
DEC are tied high, phase buildout is disabled and the device
maintains a fixed-phase relationship between the selected
input clock and the output clock during an input clock
transition. Detailed operations and timing characteristics for
this pin may be found in the Any-Frequency Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
20
INC
I
LVCMOS
Skew Increment.
A pulse on this pin increases the input to output device skew
by 1/fOSC (approximately 200 ps). There is no limit on the
range of skew adjustment by this method. If both INC and
DEC are tied high, phase buildout is disabled and the device
maintains a fixed-phase relationship between the selected
input clock and the output clock during an input clock
transition. Detailed operations and timing characteristics for
this pin may be found in the Any-Frequency Precision Clock
Family Reference Manual.
Note:
If NI_HS = 4, increment is not available.
This pin has a weak pull-down.
Table 12. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5323-B-GMR | 制造商:Silicon Laboratories Inc 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATO - Tape and Reel |
| Si5323-C-GM | 功能描述:锁相环 - PLL PIN-PROGRAMMABLE CLK MULT / JITTER ATTEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| SI5323-C-GMR | 功能描述:时钟合成器/抖动清除器 Pin-Ctrl Clk Xplier Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| SI5323-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5324 | 制造商:SILABS 制造商全称:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
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