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| 型号： | SI5855CDC-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 2/11页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH/SCHOTTKY 20V 1206-8 |
| 标准包装： | 1 |
| 系列： | LITTLE FOOT® |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 二极管（隔离式） |
| 漏极至源极电压(Vdss)： | 20V |
| 电流 - 连续漏极(Id) @ 25° C： | 3.7A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 144 毫欧 @ 2.5A，4.5V |
| Id 时的 Vgs(th)（最大）： | 1V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 6.8nC @ 5V |
| 输入电容 (Ciss) @ Vds： | 276pF @ 10V |
| 功率 - 最大： | 2.8W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SMD，扁平引线 |
| 供应商设备封装： | 1206-8 ChipFET? |
| 包装： | 标准包装 |
| 其它名称： | SI5855CDC-T1-E3DKR |
Si5855CDC
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambient
(MOSFET) b, c, f
R thJA
82
99
Maximum Junction-to-Foot (Drain) (MOSFET)
Maximum Junction-to-Ambient (Schottky) b, c, g
Maximum Junction-to-Foot (Drain) (Schottky)
R thJF
R thJA
R thJF
35
54
30
45
65
40
°C/W
Notes:
a. Based on T C = 25 °C.
b. Surface mounted on FR4 board.
c. t ≤ 5 s.
d. See Solder Profile ( www.vishay.com/doc?73257 ). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions for MOSFETs is 130 °C/W.
g. Maximum under steady state conditions for Schottky is 115 °C/W.
SPECIFICATIONS T J = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
V DS Temperature Coefficient
V GS(th) Temperature Coefficient
V DS
Δ V DS/TJ
Δ V GS(th)/TJ
V GS = 0 V, I D = - 250 μA
I D = - 250 μA
- 20
- 19
2
V
mV/°C
Gate-Source Threshold Voltage
V GS(th)
V DS = V GS , I D = - 250 μA
- 0.45
-1
V
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current a
I GSS
I DSS
I D(on)
V DS = 0 V, V GS = ± 8 V
V DS = - 20 V, V GS = 0 V
V DS = - 20 V, V GS = 0 V, T J = 55 °C
V DS ≤ - 5 V, V GS = - 4.5 V
V GS = - 4.5 V, I D = - 2.5 A
- 10
0.120
± 100
-1
- 10
0.144
ns
μA
A
Drain-Source On-State Resistance a
R DS(on)
V GS = - 2.5 V, I D = - 2.2 A
0.150
0.180
Ω
V GS = - 1.8 V, I D = - 2.0 A
0.185
0.222
Forward Transconductance a
g fs
V DS = - 10 V, I D = - 2.5 A
18
S
Dynamic b
Input Capacitance
C iss
276
Output Capacitance
Reverse Transfer Capacitance
C oss
C rss
V DS = - 10 V, V GS = 0 V, f = 1 MHz
60
43
pF
Total Gate Charge
Gate-Source Charge
Q g
Q gs
V DS = - 10 V, V GS = - 5 V, I D = - 2.5 A
V DS = - 10 V, V GS = - 4.5 V, I D = - 2.5 A
4.5
4.1
0.6
6.8
6.2
nC
Gate-Drain Charge
Q gd
1.0
Gate Resistance
R g
f = 1 MHz
1.1
5.5
11
Ω
Turn-On Delay Time
t d(on)
11
17
Rise Time
Turn-Off Delay Time
t r
t d(off)
V DD = - 10 V, R L = 5 Ω
I D ? - 2 A, V GEN = - 4.5 V, R g = 1 Ω
34
22
51
33
Fall Time
Turn-On Delay Time
t f
t d(on)
8
5
16
10
ns
Rise Time
Turn-Off Delay Time
Fall Time
t r
t d(off)
t f
V DD = - 10 V, R L = 5 Ω
I D ? - 2 A, V GEN = - 5 V, R g = 1 Ω
14
17
8
21
26
16
www.vishay.com
2
Document Number: 68910
S10-0548-Rev. B, 08-Mar-10
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