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| 型号： | SI7328DN-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 2/12页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 30V PWRPAK 1212-8 |
| 标准包装： | 3,000 |
| 系列： | TrenchFET® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 30V |
| 电流 - 连续漏极(Id) @ 25° C： | 35A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 6.6 毫欧 @ 18.9A，10V |
| Id 时的 Vgs(th)（最大）： | 1.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 31.5nC @ 4.5V |
| 输入电容 (Ciss) @ Vds： | 2610pF @ 15V |
| 功率 - 最大： | 52W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | PowerPAK? 1212-8 |
| 供应商设备封装： | PowerPAK? 1212-8 |
| 包装： | 带卷 (TR) |
New Product
Si7328DN
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambient a, b
Maximum Junction-to-Case (Drain)
t ≤ 10 s
Steady State
Steady State
R thJA
R thJC
24
65
1.9
33
81
2.4
°C/W
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. Maximum under Steady State conditions is 81 °C/W.
MOSFET SPECIFICATIONS T J = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Gate Threshold Voltage
V GS(th)
V DS = V GS , I D = 250 μA
0.6
1.5
V
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current a
I GSS
I DSS
I D(on)
V DS = 0 V, V GS = ± 12 V
V DS = 30 V, V GS = 0 V
V DS = 30 V, V GS = 0 V, T J = 55 °C
V DS ≥ 5 V, V GS = 10 V
40
± 100
1
5
nA
μA
A
Drain-Source On-State Resistance a
Forward Transconductance a
Diode Forward Voltage
R DS(on)
g fs
V SD
V GS = 10 V, I D = 18.9 A
V GS = 4.5 V, I D = 17.65 A
V DS = 15 V, I D = 18.9 A
I S = 3.2 A, V GS = 0 V
0.0055
0.0063
97
0.7
0.0066
0.0076
1.2
Ω
S
V
Dynamic b
Input Capacitance
C iss
2610
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
C oss
C rss
Q g
Q gs
Q gd
V DS = 15 V, V GS = 0 V, f = 1 MHz
V DS = 15 V, V GS = 4.5 V, I D = 18.9 A
300
140
21
7.5
2.5
31.5
pF
nC
Gate Resistance
R g
f = 1 MHz
0.5
1.2
1.8
Ω
Turn-On Delay Time
t d(on)
10
15
Rise Time
t r
V DD = 15 V, R L = 0.86 Ω
10
15
Turn-Off Delay Time
Fall Time
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
t d(off)
t f
t rr
Q rr
I D ? 17.3 A, V GEN = 10 V, R g = 1 Ω
I F = 3.2 A, dI/dt = 100 A/μs
35
8
30
18
52.5
12
60
ns
nC
Notes:
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
www.vishay.com
2
Document Number: 73960
S-81005-Rev. B, 05-May-08
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