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参数资料
| 型号： | SI7620DN-T1-GE3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 150V 13A 1212-8 |
| 产品目录绘图： | DN-T1-E3 Series 1212-8 |
| 标准包装： | 1 |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 标准 |
| 漏极至源极电压(Vdss)： | 150V |
| 电流 - 连续漏极(Id) @ 25° C： | 13A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 126 毫欧 @ 3.6A，10V |
| Id 时的 Vgs(th)（最大）： | 4.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 15nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 600pF @ 75V |
| 功率 - 最大： | 5.2W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | PowerPAK? 1212-8 |
| 供应商设备封装： | PowerPAK? 1212-8 |
| 包装： | 标准包装 |
| 产品目录页面： | 1660 (CN2011-ZH PDF) |
| 其它名称： | SI7620DN-T1-GE3DKR |
AN822
Vishay Siliconix
PowerPAK ? 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
with die on resistances around 1 m Ω and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a deriva-
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
The PowerPAK 1212-8 has a footprint area compara-
ble to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger pack-
ages are typically required solely for thermal consider-
ation, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in 2 of will yield little improve-
ment in thermal performance.
Figure 1. PowerPAK 1212 Devices
Document Number 71681
03-Mar-06
www.vishay.com
1
相关PDF资料 |
PDF描述 |
|---|---|
| SI7625DN-T1-GE3 | MOSFET P-CH D-S 30V 1212-8 PPAK |
| SI7629DN-T1-GE3 | MOSFET P-CH 20V 1212-8 PPAK |
| SI7634BDP-T1-E3 | MOSFET N-CH D-S 30V PPAK 8SOIC |
| SI7636DP-T1-GE3 | MOSFET N-CH D-S 30V PPAK 8SOIC |
| SI7655DN-T1-GE3 | MOSFET P-CH 20V D-S PPAK 1212 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SI7621DN-T1-GE3 | 功能描述:MOSFET P-CH 20V 1212-8 PPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:TrenchFET® 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件 |
| SI7623DN-T1-GE3 | 功能描述:MOSFET -20V 3.8mOhm@10V 35A P-Ch G-III RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| SI7625DN | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:P-Channel 30 V (D-S) MOSFET |
| SI7625DN-T1-GE3 | 功能描述:MOSFET -30V 7mOhm@10V 35A P-Ch G-III RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| SI7629DN | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:P-Channel 20 V (D-S) MOSFET |
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