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参数资料
| 型号： | SIC762CD-T1-GE3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 6/18页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PFC STAGE PPAK MLP66-40 |
| 标准包装： | 1 |
| 系列： | DrMOS |
| 类型： | 高端/低端驱动器 |
| 输入类型： | PWM |
| 输出数： | 1 |
| 电流 - 输出 / 通道： | 35A |
| 电源电压： | 3 V ~ 24 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | PowerPAK? MLP66-40 |
| 供应商设备封装： | PowerPAK? MLP66-40 |
| 包装： | 标准包装 |
| 其它名称： | SIC762CD-T1-GE3DKR |
SiC762CD
Vishay Siliconix
regulated high output for the buck converter. The PHASE pin
is internally connected to the switch node V SWH . This pin is
to be used exclusively as the return pin for the BOOT
capacitor. A 20.2 k Ω resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that V CIN goes to zero while V IN is still applied.
Ground connections (C GND and P GND )
P GND (power ground) should be externally connected to
C GND (control signal ground). The layout of the Printed
Circuit Board should be such that the inductance separating
the C GND and P GND should be a minimum. Transient
differences due to inductance effects between these two pins
should not exceed 0.5 V.
Control and Drive Supply Voltage Input (V DRV ,V CIN )
V CIN is the bias supply for the gate drive control IC. V DRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap switch and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one leg
tied to BOOT pin and the other tied to PHASE pin.
DEVICE TRUTH TABLE
Shoot-Through Protection and Adaptive Dead Time
(AST)
The SiC762CD has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFET are not turned on the same time. The adaptive
dead time control operates as follows. When PWM input
goes high the LS gate starts to go low after a few ns. When
this signal crosses through 1.7 V the logic to switch the HS
gate on is activated. When PWM goes low the HS gate goes
low. When the HS gate-to-source drive signal crosses
through 1.7 V the logic to turn on the LS gate is activated.
This feature helps to adjust dead time as gate transitions
change with respect to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive
holding high-side and low-side MOSFET gate low until the
input voltage rail has reached a point at which the logic
circuitry can be safely activated. The SiC762CD also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device. As an added precaution, a 20.2 k Ω resistor is
connected between GH and PHASE to provide a discharge
path for the HS MOSFET.
DSBL#
Open
L
H
H
H
H
SMOD
X
X
L
L
H
H
PWM
X
X
L
H
H
L
GH
L
L
L
H
H
L
GL
L
L
H (I L > 0), L (I L ≤ 0)
L
L
H
TRISTATE PWM VOLTAGE THRESHOLD DIAGRAM
P W M
V th_p w m_r
V th_tri_f
V th_tri_r
V th_p w m_f
GH
t TSH O
GL
t TSHO
Figure 3
www.vishay.com
6
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SIC762DB | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:Integrated DrMOS Power Stage |
| SIC769 | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:Integrated DrMOS Power Stage |
| SIC769ACD | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:Integrated DrMOS Power Stage |
| SIC769ACD-T1-GE3 | 功能描述:开关变换器、稳压器与控制器 35A 3 - 6V BUILT-IN PWM CONT RoHS:否 制造商:Texas Instruments 输出电压:1.2 V to 10 V 输出电流:300 mA 输出功率: 输入电压:3 V to 17 V 开关频率:1 MHz 工作温度范围: 安装风格:SMD/SMT 封装 / 箱体:WSON-8 封装:Reel |
| SIC769ADB | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:Integrated DrMOS Power Stage |
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