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参数资料
| 型号： | SII0680A |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP144 |
| 封装： | LQFP-144 |
| 文件页数： | 19/34页 |
| 文件大小： | 280K |
| 代理商： | SII0680A |
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SiI 0680A Data Sheet Revision 1.31-1
26
Subject to change without notice
Pin Names: PCI_CBE[3..0]
Pin Numbers: 91, 103, 114, 125
Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction,
PCI_CBE[3:0]_N define the bus command. During the data phase, PCI_CBE[3:0]_N are used as Byte Enables. Byte
Enables are valid for the entire data phase and determine which byte lanes carry meaningful data.
PCI ID Select
Pin Name: PCI_IDSEL
Pin Number: 92
This signal is used as a chip select during configuration read and write transactions.
PCI Frame Cycle
Pin Name: PCI_FRAME_N
Pin Number: 104
Cycle Frame is driven by the current master to indicate the beginning and duration of an access. PCI_FRAME_N is
asserted to indicate that a bus transaction is beginning. While PCI_FRAME_N is asserted, data transfers continue. When
PCI_FRAME_N is de-asserted, the transaction is in the final data phase or has completed.
PCI Initiator Ready
Pin Name: PCI_IRDY_N
Pin Number: 105
Initiator Ready indicates the initializing agent’s (bus master’s) ability to complete the current data phase of the transaction.
This signal is used with PCI_TRDY_N. A data phase is completed on any clock when both PCI_IRDY_N and PCI_TRDY_N
are sampled as asserted. Wait cycles are inserted until both PCI_IRDY_N and PCI_TRDY_N are asserted together.
PCI Target Ready
Pin Name: PCI_TRDY_N
Pin Number: 106
Target Ready indicates the target agent’s ability to complete the current data phase of the transaction. PCI_TRDY_N is
used with PCI_IRDY_N. A data phase is completed on any clock when both PCI_TRDY_N and PCI_IRDY_N are sampled
asserted. During a read, PCI_TRDY_N indicates that valid data is present on PCI_AD[31:0]. During a write, it indicates the
target is prepared to accept data.
PCI Device Select
Pin Name: PCI_DEVSEL_N
Pin Number: 107
Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access.
As an input, PCI_DEVSEL_N indicates to a master whether any device on the bus has been selected.
PCI Stop
Pin Name: PCI_STOP_N
Pin Number: 110
PCI_STOP_N indicates the current target is requesting that the master stop the current transaction.
PCI Parity Error
Pin Name: PCI_PERR_N
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SII0680ACL144 | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PCI to IDE/ATA |
| SII0680ACLU144 | 制造商:Silicon Image Inc 功能描述:STEELVINE HOST CONTROLLER |
| SII1000 | 制造商:SILICONIMAGE 制造商全称:SILICONIMAGE 功能描述:PanelLink Receivers |
| SII100N06 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
| SII100N12 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:NPT IGBT Modules |
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