
SiI 0680A Data Sheet Revision 1.31-1
32
Subject to change without notice
PCI Bus
Bits
Type
Description
PCI_AD[31:00]
32
I/O
PCI address/data bus
PCI_CBE[3:0]
4
I/O
PCI command/byte enables
PCI_IDSEL
1
I
PCI ID select
PCI_FRAME_N
1
I/O
PCI FRAME# signal
PCI_IRDY_N
1
I/O
PCI IRDY# signal
PCI_TRDY_N
1
I/O
PCI TRDY# signal
PCI_STOP_N
1
I/O
PCI STOP# signal
PCI_DEVSEL_N
1
I/O
PCI DEVSEL# signal
PCI_PAR
1
I/O
PCI parity bit
PCI_PERR_N
1
I/O
PCI parity error signal
PCI_SERR_N
1
OD
PCI system error signal
PCI_REQ_N
1
T
PCI bus request
PCI_GNT_N
1
I
PCI bus grant
PCI_M66EN
1
I
PCI 66 MHz enable
PCI_CLK
1
I
PCI clock
PCI_RST_N
1
I
PCI bus reset
Table 5-1: PCI Bus Signals Group
IDE Channel #0
Bits
Type
Description
IDE0_DD[15:00]
16
I/O
IDE data bus
IDE0_CS0_N
1
I/O
IDE chip select
IDE0_CS1_N
1
I/O
IDE chip select
IDE0_DA0
1
I/O
IDE device address
IDE0_DA1
1
I/O
IDE device address
IDE0_DA2
1
I/O
IDE device address
IDE0_DIOR_N
1
I/O
IDE device IO read
IDE0_DIOW_N
1
I/O
IDE device IO write
IDE0_DMACK_N
1
I/O
IDE DMA acknowledge
IDE0_CBLID_N
1
I
IDE cable ID
IDE0_INTRQ
1
I
IDE interrupt request
IDE0_IORDY
1
I
IDE IO channel ready
IDE0_AT_REXT
1
I/O
IDE external bias circuit
IDE0_DMARQ
1
I
IDE DMA request
IDE0_RST_N
1
I/O
IDE reset
Table 5-2: IDE Channel #0 Signals Group
IDE Channel #1
Bits
Type
Description
IDE1_DD[15:00]
16
I/O
IDE data bus
IDE1_CS0_N
1
I/O
IDE chip select
IDE1_CS1_N
1
I/O
IDE chip select
IDE1_DA0
1
I/O
IDE device address
IDE1_DA1
1
I/O
IDE device address
IDE1_DA2
1
I/O
IDE device address
IDE1_DIOR_N
1
I/O
IDE device IO read
IDE1_DIOW_N
1
I/O
IDE device IO write
IDE1_DMACK_N
1
I/O
IDE DMA acknowledge
IDE1_CBLID_N
1
I
IDE cable ID
IDE1_INTRQ
1
I
IDE interrupt request
IDE1_IORDY
1
I
IDE IO channel ready
IDE1_AT_REXT
1
I/O
IDE external bias circuit