参数资料
型号: SIP11203DLP-T1-E3
厂商: Vishay Siliconix
文件页数: 11/18页
文件大小: 0K
描述: IC REG CTRLR ISO PWM MLP44-16
标准包装: 2,500
PWM 型: 控制器
输出数: 1
电源电压: 5.5 V ~ 13 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: PowerPAK? MLP44-16
包装: 带卷 (TR)
SiP11203, SiP11204
Vishay Siliconix
POWER-DOWN DRIVER OPERATION (CONT’D)
The internal pull-downs ensure that the synchronous
rectifiers are in the off state before the bias supply to
the IC has collapsed (See Figure 5). Since these pull-
downs have a lower current-sinking capability than the
main OUTA and OUTB drivers, they can cause the
rectifier MOSFETs to transition from full conduction to
the off state via their linear region of operation. This
soft turn-off allows the use of the gradually increasing
rectifier channel impedances to help damp LC
oscillations that might otherwise occur at the
converter's output. The gate pull-down current value,
and therefore the interval during which the rectifier
MOSFETs are in transition from fully on to fully off, is
programmed by the resistor from RPD to ground. This
current is given by I PULL-DO W N = 200* V REFINT /R PD .
This programmability allows the choice of a gate
discharge time which best accommodates the design
variables of L OUT , C OUT , and synchronous rectifier
MOSFET characteristics.
The power-down latch will be reset, and a soft-start
cycle will occur, when the logical and of two conditions
is true:
? The voltage on the V REF capacitor is 20 % (245 mV)
of its nominal 1.225 V, and
? The exclusive-or of INA and INB is true, that is, one
input is in low while the other is high.
Note that low values of R PD will increase the main
supply current. It is recommended that R PD be kept
?? 15 k ? to prevent excessive power dissipation.
Figure 6. Power Down Detect and “Soft” Turn-Off
SYNCHRONOUS RECTIFIER PHASE-IN AND
RISING EDGE DELAY
The SiP11203/SiP11204 has the ability to “phase in”
the synchronous rectifiers at start-up. This causes the
rectifier MOSFETs to initially be used as conventional
PN (or Schottky) diodes, then as synchronous
rectifiers for an increasing percentage of each
switching cycle, until finally they are operating
completely as synchronous switches. W hen this
feature of the IC is used, the resistance R DEL , which is
connected between the R DEL pin and ground,
determines the time required for the transition from
diode-mode operation to fully synchronous
rectification.
To achieve this phase-in of the synchronous rectifiers,
an internally extended propagation delay ( ? T DEL ) is
V I N
V L
I N A/B
2.5 V
C PD
V REF
SHUTDOW
RESTART
introduced between the rising edge of each input (INA
or INB) and the rising edge of the corresponding output
(OUTA or OUTB). The length of this delay is
proportional to R DEL and inversely proportional to
V REF : ? T DEL ?? (1.5 ns x R DEL x 1.225 V)/(1 k ? x V REF ).
Therefore ? T DEL decreases throughout the interval
during which V REF is rising (i.e., during the time
following converter start-up or a SiP11203/SiP11204
soft-start event). W hen the phase-in period has ended,
the final high-going propagation delay is T DEL(FINAL) =
T pdr + T DEL(FINAL) = T pdr + [(1.5 ns x R DEL )/1 k ?? ], as
shown in the typical curves.
OUTA/B
Figure 5. The shutdown sequence of SiP11203/SiP11204
prevents the synchronous MOSFET of a half-bridge converter
from discharging a prebiased output when supplied power is
removed
Document Number: 73868
S11-0975–Rev. C, 16-May-11
www.vishay.com
11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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