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参数资料
| 型号： | SIP11203DLP-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 3/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR ISO PWM MLP44-16 |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 电源电压： | 5.5 V ~ 13 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | PowerPAK? MLP44-16 |
| 包装： | 带卷 (TR) |
SiP11203, SiP11204
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
5.5 V ? V IN ? 13 V
Limits
Parameter
Symbol
T A = - 40 °C to 85 °C
Min. a
Typ. b
Max. a
Unit
Logic Inputs - IN A and IN B
Input High
Input Low
Input Resistance
Input Frequency Range (INA and
INB)
V IH
V IL
R IN
f IN
Rising
Falling
V IN = 13 V, 13 V at INA and/or INB
(Note c)
4.0
3.0
100
2.5
2.1
3.8
1.0
4.5
500
V
k ?
kHz
Error Amplifier - DC Electrical Characteristics
Voltage Gain
Common Mode Rejection Ratio
A V
CMRR
20 log ( ? V OUT / ? V OS ) for V OUT = 0.5 V to 3.0 V
Input CMR = 0 V to 3.5 V
65
60
70
65
dB
Input Offset Voltage
V OS Temperature Coefficient
Input Bias Current
Input Offset Current
V OS
TC3
I BIAS
I OS
V CM = 1.225 V, R LOAD = 10 k ? to V CM
(Note c)
V CM = 1.225 V
(I EA+ ) - (I EA- ), (Note c)
±3
30
2
± 0.3
± 15
10
mV
μV/°C
nA
Output Voltage
Output Current
V OL
V OH
I OH
I OL
Output sinking 0.8 mA
Output sourcing 0.8 mA
Sourcing, EA OUT = 1.0 V, EA+ overdrive = 500 mV
Sinking, EA OUT = 2.5 V, EA+ overdrive = 500 mV
3.0
3.5
0.8
225
3.45
4.7
1.3
400
mV
V
mA
Error Amplifier - AC Electrical Characteristics
Gain-Bandwidth Product
Slew Rate
B W
SR+
SR-
(Note c)
Rising, R LOAD = 2 k ? II 1 nf to Ground
Falling, R LOAD = 2 k ? II 1 nf to Ground
1
0.75
1
MHz
V/μs
MOSFET Drivers
Driver Impedance
Peak Drive Current
Rise Time
Fall Time
R D(SOURCE)
R D(SINK)
R D(SOURCE)
R D(SINK)
I PK(SOURCE)
I PK(SINK)
I PK(SOURCE)
I PK(SINK)
t r
t f
V IN = 5.5 V, I OUT = 100 mA, T J = 25 °C
V IN = 7.5 V, I OUT = 100 mA, T J = 25 °C
V IN = 5.5 V, T J = 25 °C (Note c)
V IN = 7.5 V, T J = 25 °C (Note c)
10 % to 90 %, V IN = 5.5 V, C LOAD = 6 nF, (Note c)
10 % to 90 %, V IN = 7.5 V, C LOAD = 6 nF, (Note c)
90 % to 10 %, V IN = 5.5 V, C LOAD = 6 nF, (Note c)
90 % to 10 %, V IN = 7.5 V, C LOAD = 6 nF, (Note c)
2.3
1.5
2.1
1.4
1.2
2.4
2.2
4.0
45
42
35
32
3.7
2.4
3.4
2.2
?
A
t pdr
INA/INB rising to OUTA/OUTB rising, 50 % to 50 %
V IN = 5.5 V, R DEL connected to V L , C LOAD = 0 nF
20
32
55
ns
IN to OUT Propagation Delay
Additional Rising Edge OUT A/B
Delay vs. R DEL
Power-down Detection Timeout
t pdf
? t DELAY
t PDDET
INA/INB falling to OUTA/OUTB falling, 50 % to 50 %
V IN = 5.5 V, R DEL connected to V L , C LOAD = 0 nF
R DEL connected to V L
R DEL = 25 k ? to GND, C LOAD = 0 nF (Note d)
IN A and IN B low to OUT A/OUT B low
R PD = 25 k ? , C PD = 1 nF (Note c)
20
28
34
38
25
55
0
48
μs
No forcing voltage on V IN or V L , both V IN and V L
Power-up Output Hold-off Current
I HOFF
bypassed by 1 μF to GND, INA or INB = 5 V, other
input = 0 V, force 1 V at active output (A or B)
350
530
mA
Document Number: 73868
S11-0975–Rev. C, 16-May-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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