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参数资料
| 型号： | SL2309ZI-1T |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER 140MHZ 9CH3.3V 16TSSOP |
| 标准包装： | 2,500 |
| 系列： | EProClock® |
| 类型： | * |
| PLL： | 带旁路 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:9 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 140MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
Rev 1.3, July 31, 2007
Page 8 of 12
SL2309
External Components & Design Considerations
Typical Application Schematic
SL2309
CL
0.1
μF
0.1
μF
CLKIN
CLKOUT
CLKA1
CLKB4
GND
S1
S2
VDD
1
4
13
9
8
5
12
11
2
16
VDD
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the capacitor s
on the component side of the PCB as close to the VDD pins as possible. The PCB trace to the VDD pin and to the GND
via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and
the load is over 1 inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination
resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and
sees an additional 2 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the
load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the
capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and
B clocks and CLKIN.
For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
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