参数资料
型号: SM3-19.44M
厂商: Connor-Winfield
文件页数: 11/36页
文件大小: 0K
描述: IC MOD TIMING 19.440MHZ STATUM 3
标准包装: 1
系列: SM3
类型: 定时模块,系统时钟
PLL:
主要目的: 以太网,ADM,DSLAM,SONET/SDH,Stratum,TDM
输入: LVCMOS
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 4:3
差分 - 输入:输出: 无/无
频率 - 最大: 19.44MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 32-DIP 模块
包装: 管件
其它名称: CW642
SM3 19.44M
SM319.44M
SM3 Data Sheet #:
TM052
Page 19 of 36 Rev: 06 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Performance Definitions
Jitter and Wander – Jitter and wander are defined respectively as “the short-term and long-term variations of the significant
instants of a digital signal from their ideal positions in time”. They are therefore the phase or position in time modulations of a digital
signal relative to their ideal positions. These phase modulations can in turn be characterized in terms of their amplitude and frequency.
Jitter is defined as those phase variations at rates above 10Hz, and wander as those variations at rates below 10Hz.
Fractional frequency offset and drift – The fractional frequency offset of a clock is the ratio of the frequency error (from the
nominal or desired frequency) to the desired frequency. It is typically expressed as (n parts in 10X), or (n x 10-X). Drift is the measure
of a clock’s frequency offset over time. It is expressed the same way as offset.
Time Interval Error (TIE) – TIE is a measure of wander and is defined as the variation in the time delay of a given signal relative
to an ideal signal over a particular time period. It is typically measured in nS. TIE is set to zero at the start of a measurement, and thus
represents the phase change since the beginning of the measurement.
Maximum Time Interval Error (MTIE) – MTIE is a measurement of wander that finds the peak-to-peak variations in the time delay
of a signal for a given window of time, called the observation interval (t). Therefore it is the largest peak-to-peak TIE in any observation
interval of length t within the entire measurement window of TIE data. MTIE is therefore a useful measure of phase transients,
maximum wander and frequency offsets. MTIE increases monotonically with increasing observation interval.
Time Deviation (TDEV) – TDEV is a measurement of wander that characterizes the spectral content of phase noise. TDEV(t is the
RMS of filtered TIE, where the bandpass filter is centered on a frequency of 0.42/t.
SM3 Performance
Input Jitter Tolerance – Input jitter tolerance is the amount of jitter at its input a clock can tolerate before generating an indication
of improper operation. GR-1244 and ITU-813 requirements specify jitter amplitude v.s. jitter frequency for jitter tolerance. The SM3
device provides jitter tolerance that meets the specified requirements.
Input Wander Tolerance – Input wander tolerance is the amount of wander at its input a clock can tolerate before generating an
indication of improper operation. GR-1244 and ITU-813 requirements specify input wander TDEV vs. Integration Time as shown below.
Integration Time, (seconds)
TDEV (ns)
0.05
τ <10
100
10<
τ<1000
31.6x
τ 0.5
1000
τ
N/A
The SM3 device provides wander tolerance that meets these requirements.
Phase Transient Tolerance – GR-1244 specifies maximum reference input phase transients that a clock system must tolerate
without generating an indication of improper operation. The phase transient tolerance is specified in MTIE(nS) v.s. observation time
from .001 to 100 seconds, as shown below.
Observation time S (Seconds)
MTIE (ns)
0.001326
≤S<0.0164
61,000xS
0.0164<S<1.97
925+4600xS
1.97
≤S
10,000
The SM3 will tolerate all reference input transients within the GR-1244 specification.
Free Run Frequency Accuracy – Free Run frequency accuracy is the maximum fractional frequency offset while in Free Run
mode. It is determined by the accuracy of the internal clock.
Hold Over Frequency Stability – Hold Over frequency stability is the maximum fractional frequency offset while in Hold Over
mode. It is determined by the stability of the internal clock.
Performance Specifications
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