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参数资料
| 型号： | SM320C50HFGM66 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-BIT, 66 MHz, OTHER DSP, CQFP132 |
| 封装： | TIE BAR, CERAMIC, QFP-132 |
| 文件页数： | 4/35页 |
| 文件大小： | 536K |
| 代理商： | SM320C50HFGM66 |
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CLOCK CHARACTERISTICS AND TIMING
The ’C50 can use either its internal oscillator or an external frequency source for a clock. The clock mode is
determined by the CLKMD1 and CLKMD2 pins. Table 1 outlines the selection of the clock mode by these pins.
Table 1. Clock Mode Selection
CLKMD1
CLKMD2
CLOCK SOURCE
1
0
External divide-by-one clock option
0
1
Reserved for test purposes
1
External divide-by-two option or internal divide-by-two clock option
with an external crystal
0
External divide-by-two option with the internal oscillator disabled
internal divide-by-two clock option with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2 /CLKIN. The frequency of CLKOUT1
is one-half the crystal’s oscillating frequency. The crystal should be in either fundamental or overtone operation
and parallel resonant, with an effective series resistance of 30
and a power dissipation of 1 mW; it should be
specified at a load capacitance of 20 pF. Overtone crystals require an additional tuned LC circuit. Figure 4 shows
an external crystal (fundamental frequency) connected to the on-chip oscillator.
recommended operating conditions for internal divide-by-two clock option
’320C50-50
’320C50-66
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
fx
Input clock frequency
0
50
0
66
MHz
C1, C2
Load capacitance
10
pF
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz but is tested at a minimum of 3.3 MHz to meet device test time requirements.
X1
X2 /CLKIN
C1
C2
Crystal
Figure 4. Internal Clock Option
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