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参数资料
| 型号： | SM320MCM42CHFNM40 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, CQFP408 |
| 封装： | TIE-BAR, CERAMIC, QFP-408 |
| 文件页数： | 13/22页 |
| 文件大小： | 358K |
| 代理商： | SM320MCM42CHFNM40 |
Product Folder: SMJ320MCM42D, Dual SMJ320C40 Multichip Module, Digital Signal Processor
Keyword
Part Number
PRODUCT SUPPORT: COMPATIBLE DATA CONVERTERS
SMJ320MCM42D, Dual SMJ320C40 Multichip Module, Digital Signal Processor
DEVICE STATUS: ACTIVE
PARAMETER NAME
SMJ320MCM42D
Voltage Nodes (nom) (V) 5
FEATURES
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Performance:
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80 Million Floating-Point Operations Per Second (MFLOPS) With 496-MBps-Burst I/O Rate for 40-MHz Modules
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Zero-Wait-State Local Memory for Each Processor
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Organization:
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128K-Word × 32-Bit Static Random-Access Memory (SRAM) (SMJ320MCM42D)
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256K-Word × 32-Bit SRAM (SMJ320MCM42C)
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Compliant With MIL-PRF-38535 QML
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Dual C40 Performance With Local Memory Requiring Only 8.7 Square Inches of Board Space
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Enhanced Performance Offered By Multichip-Module Solution
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SMJ320MCM42C
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67% Reduction in Number of Interconnects
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54% Reduction (Minimum) in Board Area
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Estimated 38% Reduction in Power Dissipation Due to Reduced Parasitic Capacitance and Interconnect Lengths
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SMJ320MCM42D
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56% Reduction in Number of Interconnects
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30% Reduction (Minimum) in Board Area
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Estimated 20% Reduction in Power Dissipation Due to Reduced Parasitic Capacitance and Interconnect Lengths
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Four Memory Ports for High Data Bandwidth
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Two Full 2G-Word External Buses
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Two Internal Buses Mapped to Memory
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128K-Word × 32-Bit SRAM for Each C40 Local Bus (SMJ320MCM42D)
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256K-Word × 32-Bit SRAM for Each C40 Local Bus (SMJ320MCM42C)
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Ten External Communication Ports for Direct Processor-to-Processor Communication
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IEEE-1149.1
(JTAG) Boundary-Scan Compatible
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408-Lead Ceramic Quad Flatpack Package (HFN Suffix)
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Operating Free-Air Temperature Ranges:
–55°C to 125°C . . . (Military)
0°C to 70°C . . . (Commercial)
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Communication-Port Connection Provided Between C40s for Interprocessor Communication
IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture
DESCRIPTION
The 42 dual C40 multichip module (MCM) contains two SMJ320C40 digital signal processors (DSPs) with 128K words × 32 bits (42D) or 256K words × 32 bits (42C) of zero-wait-state SRAMs mapped to each
local bus. Global address and data buses with two sets of control signals are routed externally for each processor, allowing external memory to be accessed. The external global bus provides a continuous
address reach of 2G words.
The dual C40 configuration allows standard microprocessor initialization using the bootstrap loader. Both reset-vector-control terminals are brought out to external terminals for each processor. A single CLKIN
line and a RESET line feed both processors in parallel, minimizing clock skew and allowing easy synchronization for interlocked operations.
file:///G|/imaging/BITTING/CPL/20030422/04212003_9/TXII/042120003_HTML/smj320mcm42d.html (1 of 3) [23-Apr-03 5:18:53 PM]
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