参数资料
型号: SM561BZ
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: 时钟产生/分配
英文描述: 166 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8
封装: SOIC-8
文件页数: 5/10页
文件大小: 75K
代理商: SM561BZ
Spread Spectrum Clock Generator
CYPRESS SEMICONDUCTOR CORPORATION 525 Los Coches St.
Document#: 38-07021 Rev. **
05/04/2001
MILPITAS, CA 95035 TEL: 408-263-6300, FAX 408-263-6571
Page 4 of 10
http://www.cypress.com
APPROVED PRODUCT
SM561
Frequency and Spread % Selection
54– 108 MHz (Low Range)
Input
Frequency
(MHz)
S1=M
S0=M
S1=M
S0=0
S1=1
S0=0
S1=0
S0=0
S1=0
S0=M
54– 60
3.6
3.1
2.6
2.1
1.8
60 – 70
3.5
3.0
2.5
2.0
1.7
70 – 80
3.3
2.8
2.4
1.9
1.6
80 - 100
3.0
2.5
2.1
1.7
1.4
100 - 108
2.6
2.3
1.9
1.5
1.3
108 – 166 MHz (High Range)
Input
Frequency
(MHz)
S1=1
S0=M
S1=0
S0=1
S1=1
S0=1
S1=M
S0=1
108 – 120
2.3
1.7
1.1
0.9
120 – 130
2.3
1.7
1.1
0.9
130 – 140
2.3
1.7
1.1
0.9
140 – 150
2.2
1.6
1.1
0.9
150 - 166
2.1
1.5
1.0
0.8
Table 2. Frequency and Spread % Selection
Tri-Level Logic
With binary logic, 4 states can be programmed with 2 control lines where as Tri-Level Logic can program 9 logic
states using 2 control lines. Tri-Level Logic in the SM561 is implemented by defining a third logic state in addition
to the standard logic “1” and “0”. Pin 6 and 7 of the SM561 recognize a logic state by the voltage applied to the
respective pin. These states are defined as “0” (Low), “M” (Middle) and “1” (One). Each of these states have a
defined voltage range that is interpreted by the SM561 as a “0”, “M” or “1” logic state. Refer to table 5 for voltage
ranges for each logic state.
By using two equal value resistors (typically 20K) the “M” state can be easily
programmed. Pins 6 or 7 can be tied directly to ground or VDD for Logic “0” or “1” respectively.
See examples below;
Select the
Frequency and
Spread %
desired and then
set S1, S0 as
indicated.
Select the
Frequency and
Spread %
desired and then
set S1, S0 as
indicated.
VDD = 3.3 VDC
SM561
5
6
7
SM561
5
6
7
1.65 VDC
0 VDC
7
6
5
SM561
EX. 1
EX. 2
EX. 3
20K
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