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参数资料
| 型号： | SM561BZ |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 166 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8 |
| 封装： | SOIC-8 |
| 文件页数： | 6/10页 |
| 文件大小： | 75K |
| 代理商： | SM561BZ |
Spread Spectrum Clock Generator
CYPRESS SEMICONDUCTOR CORPORATION 525 Los Coches St.
Document#: 38-07021 Rev. **
05/04/2001
MILPITAS, CA 95035 TEL: 408-263-6300, FAX 408-263-6571
Page 5 of 10
http://www.cypress.com
APPROVED PRODUCT
SM561
Absolute Maximum Ratings
Supply Voltage(AVDD or DVDD): +6V
AVDD - DVDD: +/-300mV
AGND - DGND: +/-300mV
Junction Temperature (10-sec. soldering): +300
°C
Operating Temperature: 0 to 70
°C
Storage Temperature: -65 to +150
°C
Note: Operation at any Absolute Maximum Rating is not implied.
DC Electrical Characteristics
Test Conditions: VDD=3.3V, Temp. =25
°C and CL (Pin 4) =15pF, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
VDD
Power Supply Range
2.97
3.3
3.63
V
+/- 10 %
VINH
Input High Voltage
0.85VDD
VDD
V
S0 and S1 only.
VINM
Input Middle Voltage
0.40VDD 0.50VDD 0.60VDD
V
S0 and S1 only.
VINL
Input Low Voltage
0.0
0.15VDD
V
S0 and S1 only.
VOH1
Output High Voltage
2.4
-
V
IOH = 6 ma
VOH2
Output High Voltage
2.0
-
V
IOH = 20 ma
VOL1
Output Low Voltage
-
0.4
V
IOH = 6 ma
VOL2
Output Low Voltage
-
1.2
V
IOH = 20 ma
Cin1
Input Capacitance
3
4
5
pF
Xin/CLK (Pin 1)
Cin2
Input Capacitance
6
8
10
pF
Xout (Pin 8)
Cin2
Input Capacitance
3
4
5
pF
S0, S1, SSCC (Pins 7,6,5)
IDD1
Power Supply Current
-
35
45
ma
FIN = 65 MHz
IDD2
Power Supply Current
-
50
55
ma
Fin = 166 MHz
Table 5
Electrical Timing Characteristics
Test Conditions: VDD=3.3V, T=25
°C and CL=15pF unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit Conditions
ICLKFR
Input Clock Frequency Range
54
166
MHz VDD = 3.30V
Trise
Clock Rise Time (Pin 4)
1.2
1.4
1.6
ns
SSCLK1 @ 0.4 – 2.4V
Tfall
Clock Fall Time (Pin 4)
1.2
1.4
1.6
ns
SSCLK1 @ 0.4 – 2.4V
DTYin
Input Clock Duty Cycle
20
50
80
%
XIN/CLK (Pin 1)
DTYout
Output Clock Duty Cycle
45
50
55
%
SSCLK1 (Pin 4)
JCC1
Cycle-to-Cycle Jitter
-
125
175
ps
Fin < 140 MHz
JCC2
Cycle-to-Cycle Jitter
-
150
200
ps
Fin > 140 MHz
Table 6
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