SM8521
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Clock change register (CKKC)
Clock change register CKKC is an 8-bit readable/
writable register containing the control of system
clock change and the setting of warming up period
after waking up from the STOP mode.
Clock change register CKKC is initialized to 00
H
after hardware reset.
Bit 7
0
Bit 7 : Clock change enable bit (FCPUEN)
Bit 6 : Main-clock stopped bit (MCKSTP)
Main-clock stopped allows switching to sub-clock
used as system clock.
Bits 5 to 3 : System clock selection bits
(FCPUS2-FCPUS0)
Under the bit FCPUEN = ‘1’, if executes the
STOP instruction, the bits will be valid.
BIT
SYSTEM CLOCK FREQUENCY
000
System clock = (1/32) x main-clock
001
System clock = (1/16) x main-clock
010
System clock = (1/8) x main-clock
011
System clock = (1/4) x main-clock
100
System clock = (1/2) x main-clock
Bit 2 : Reserved bit (TFCPU)
Always write ‘0’ to this position. Writing a ‘1’
produces unrealiable operation.
Bits 1 to 0 : Warming up selection bits
(WUPS1-WUPS10)
The bits are able to set the warming up period
of after wake up from STOP mode.
WARMING UP PERIOD AFTER STOP
MODE RELEASES
(when main-clock (f
CK
) = 10 MHz)
00
2
18
x main-clock period (26.21 ms)
01
2
17
x main-clock period (13.10 ms)
10
2
16
x main-clock period (6.553 ms)
11
2
15
x main-clock period (3.276 ms)
101, 110
111
Reserved
System clock = (1/2) x sub-clock
BIT
FCPUEN MCKSTP FCPUS2 FCPUS1 FCPUS0
TFCPU
WUPS1
WUPS0
Fig. 8 SM8521 Clock System (Equivalent Circuit for Clock System Peripheral Blocks)
f
CK
Main-clock
1/2
1/2
1/2
1/2
1/2
1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
CG
System clock f
SYS
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
5
S
f
32K
f
32K
f
CK
/4
f
CK
/8 f
CK
/16 f
CK
/32
System clock frequency control
Prescaler PRS0 (frequency divider on f
CK
/2)
Prescaler PRS1 (frequency divider on f
32K
)
Sub-clock
fc
10
fc
11
fc
12
fc
13
fc
14
fc
15
fc
16
fx
1
fx
2
fx
3
fx
4
fx
5
fx
6
fx
7
fx
8
8
f
CK
/2
f
CK
/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
fc
12
fc
13
fc
14
fc
15
Prescaler PRS2 (frequency divider on fc
10
)
Warming up counter (frequency divider on fc
10
)
For warming
up counter
8
To function blocks
BIT
0
1
CONTENT
Disables system clock speed change
Enables system clock speed change
BIT
0
1
CONTENT
Main-clock operation
Main-clock stop