SM8521
- 32 -
CLOCK TIMER REGISTER
CLKT (Clock timer register)
Bit 7
0
Bit 7 : Run/reset
BIT
0
1
Bit 6 : Minute/second
BIT
0
1 second
1
1 minute
Bits 5 to 0 : Value of counter (read only)
Watchdog Timer Register (WDT)
PRS2 (Prescaler 2)
Prescaler PRS2 generates the count clock to
watchdog timer counter WDT.
The following conditions are to clear all bits of
prescaler PRS2.
When hardware reset.
When watchdog timer counter WDT stopped.
When counter WDT is cleared by writing ‘1’ to
the bit WDTCR (bit 3 : WDTC).
Prescaler PRS2 divides the frequency derived from
input clock fc
10
(204.8 μs : main-clock = 10 MHz),
then fc
11
-fc
15
are output.
WDT (Watchdog timer counter register)
Watchdog timer counter WDT is an 8-bit read only
register which counts up from input clock.
WDTC (Watchdog timer control register)
Watchdog timer control WDTC is an 8-bit read only
register which sets watchdog timer to start/stop,
counter clear designation, and selects the count
clock.
Bit 7
0
Bit 7 : Watchdog timer start/stop bit (WDTST)
BIT
0
Timer stop [WDT is cleared.]
1
Timer start
Bit 6 :
Operation select while watchdog timer overflow
(WDTRN)
BIT
CONTENT
0
Hardware reset
1
Non-maskable interrupt
Bits 5 to 4 : set ‘0’.
Bit 3 : Counter clear bit (WDTCR) [write only bit]
BIT
0
No clear
1
Only in writing operation, WDT is cleared.
Bits 2 to 0 : Watchdog timer counter clock selection
bits (WCNT2-WCNT0)
BIT
COUNT CLOCK
000
fc
12
(819 μs
1
)
001
fc
13
(1.639 ms
1
)
010
fc
14
(3.278 ms
1
)
011
fc
15
(6.578 ms
1
)
100
fx
5
(0.976 ms
2
)
101
fx
6
(1.95 ms
2
)
110
fx
7
(3.90 ms
2
)
111
fx
8
(7.81 ms
2
)
1 The value in ( ) is the period when main-clock is
10 MHz.
2 The value in ( ) is the period when sub-clock is
32.768 kHz.
WDTST
WDTRN
-
-
WDTCR WCNT2 WCNT1 WCNT0
1/2 1/2 1/2 1/2 1/2
fc
11
fc
12
fc
13
fc
14
fc
15
PRS2 fc
2
CONTENT
CONTENT
STATUS
STATUS
Counter reset
Run