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参数资料
| 型号： | SME5434PCI-440 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 440 MHz, RISC PROCESSOR, XMA |
| 封装： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件页数： | 1/30页 |
| 文件大小： | 393K |
| 代理商： | SME5434PCI-440 |
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Preliminary
DATA SHEET
1
SME5431PCI-360
SME5434PCI-440
UltraSPARC II
i CPU Module
360/440MHz CPU; 0.25 to 2 MB L2 cache; UPA64S, 66MHz PCI Interfaces
DESCRIPTION
The UltraSPARC-IIi CPU Modules provide high-performance, SPARC v9 architecture computing on a mez-
zanine-style conguration consisting of an UltraSPARC-IIi microprocessor, L2 cache SRAMs, and high speed
clock logic. CPU-integrated memory and bus controllers drive signals to two external connectors.
These two UltraSPARC IIi CPU modules run at up to 440 MHz and simplify system-board design while pro-
viding upgradeable system performance.
The module provides EDO DRAM memory control, a UPA64S interface, and a PCI 2.1-compatible bus. The
DRAM data bus is ECC protected and multiplexed from 72 pins to 144 memory bits using data transceivers
on the system board controlled by the microprocessor. It uses 3.3 volt CMOS signaling. The UPA64S slave
interface operates at 1/4 CPU frequency, also uses 3.3 volt signalling and is compatible with Sun’s FFB Cre-
ator and AFB Elite graphics boards. The 66 MHz, 32-bit PCI bus is normally connected to Sun’s Advanced
PCI Bridge (APB) to provide two separate 32-bit, 33 MHz PCI 2.1-compatible buses.
Features
Benets
High performance UltraSPARC-IIi CPU
18.7 SPECint95 (est.), 21.1 SPECfp95 (est.) at 440 MHz, 2 MB
L2 cache
SPARC V9 architecture
64-bit performance with binary compatibility with v8 and v9
application programs
Implements VIS
Instruction Set
Computing pipeline for 3D graphics, imaging,
compression/decompression, and network trafc
Double clocked 8-byte memory bus
Reduced pin count and peak memory bandwidth of up to 586
MB/s at 440 MHz
2-MB second-level cache clocked at 1/2 CPU
frequency
L2-cache bandwidth on module of up to 1.76 GB/s at 440 MHz
Components operate at 3.3V LVTTL and 1.9V HSTL
High bus speeds, lower power, and 3.3V LVTTL-compatible I/O
66 MHz PCI 2.1-compatible bus
Integrated interface simplies I/O system design
130 mm x 100 mm x 45 mm (height) form factor
Small-footprint, upgradeable
JTAG (IEEE 1149) boundary-scan interface
Board-level testability
System interface through two impedance-controlled
connectors
High-performance and reliable signal integrity
September 2001
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