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参数资料
| 型号： | SME5434PCI-440 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 440 MHz, RISC PROCESSOR, XMA |
| 封装： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件页数： | 2/30页 |
| 文件大小： | 393K |
| 代理商： | SME5434PCI-440 |
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10
SME5431PCI-360
SME5434PCI-440
Preliminary
360/440MHz CPU; 0.25 to 2 MB L2 cache; UPA64S, 66MHz PCI Interfaces
UltraSPARC IIi CPU Module
September 2001
Sun Microsystems, Inc
MEM_ECC[7:0]
I/O
Memory ECC bits
MEM_ADDR[12:0]
O
Memory Address: (row and column)
XCVR_OEA_L
O
Transceiver Output Enable A: active low
XCVR_OEB_L
O
Transceiver Output Enable B: active low
XCVR_SEL_L
O
Transceiver Select; Active low: picks high or low half of read data
XCVR_WR_CNTL[1:0]
O
Transceiver Write Control: Controls lock enables on internal registers
XCVR_RD_CNTL[1:0]
O
Transceiver Read Control: control clock enables on internal registers
XCVR_CLK[2:0]
O
Transceiver Clock: all data and control signals are registered by these clocks; multiple
outputs to minimize loading effects of six transceivers; should be parallel terminated to
GND on the system board
UPA64S Interface
Symbol
Type
Name and Function
S_REPLY[2:0]
O
S Reply: encoded command that indicates arrival of write data on MEM_DATA[63:0], or
command to drive MEM_DATA[63:0] with read data
P_REPLY[1:0]
I
P Reply: Encoded command that indicates consumption of prior write, or ability to
provide read data.
SYSADR[28:0]
O
System Address: sends two cycle-address packets to the UPA64S slave, or provides
internal state debug information.
ADR_VLD
O
Address Valid: asserted during rst cycle of two cycle address packet.
Memory and Transceivers Interface (Continued)
Symbol
Type
Name and Function
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