参数资料
型号: SME5434PCI-480
元件分类: 微控制器/微处理器
英文描述: 64-BIT, 480 MHz, RISC PROCESSOR, XMA
封装: 130 X 100 MM, 45 MM HEIGHT MODULE
文件页数: 1/34页
文件大小: 418K
代理商: SME5434PCI-480
Preliminary
DATA SHEET
1
SME5431PCI-360
SME5434PCI-440
SME5434PCI-480
UltraSPARC-II
i CPU Module
360/440/480MHz CPU; 0.25 to 2 MB L2 cache, UPA64S, 66MHz PCI
DESCRIPTION
The SME5431PCI and SME5434PCI UltraSPARC-IIi CPU Modules provide high-performance, SPARC v9
architecture computing on a mezzanine-style conguration consisting of an SME1430 UltraSPARC-IIi Micro-
processor [1], L2 cache SRAMs, and high speed clock logic. CPU-integrated memory and bus controllers drive
signals to two external connectors.
These three UltraSPARC i-series CPU modules run at up to 480 MHz and simplify system-board design while
providing upgradeable system performance. They include second-generation SME1430LGA UltraSPARC IIi
microprocessors which differ slightly from the SME1040 UltraSPARC-IIi microprocessors. See page 12.
The module provides EDO DRAM memory control, a UPA64S interface, and a PCI 2.1-compatible bus. The
DRAM data bus is ECC protected and multiplexed from 72 pins to 144 memory bits using data transceivers
on the system board controlled by the microprocessor. It uses 3.3 volt CMOS signaling. The UPA64S slave
interface operates at 1/4 CPU frequency, also uses 3.3 volt signalling and is compatible with Sun’s FFB Cre-
ator and AFB Elite graphics boards. The 66 MHz, 32-bit PCI bus is normally connected to Sun’s Advanced
PCI Bridge (APB) to provide two separate 32-bit, 33 MHz PCI 2.1-compatible buses.
1. See URL: http://www.sun.com/microelectronics/UltraSPARC/ for all UltraSPARC-i series products
Features
Benets
High performance UltraSPARC-IIi CPU
20.2 SPECint95 (est.),22.5 SPECfp95 (est.) at 480 MHz, 2 MB
L2 cache
SPARC V9 architecture
64-bit performance with binary compatibility with v8 and v9
application programs
Implements VIS
Instruction Set
Computing pipeline for 3D graphics, imaging,
compression/decompression, and network trafc
Double clocked 8-byte memory bus
Reduced pin count and peak memory bandwidth of up to 639
MB/s at 480 MHz
2-MB second-level cache clocked at 1/2 CPU
frequency
L2-cache bandwidth on module of up to 1.9 GB/s at 480 MHz
Components operate at 3.3V LVTTL and 1.9V HSTL
High bus speeds, lower power, and 3.3V LVTTL-compatible I/O
66 MHz PCI 2.1-compatible bus
Integrated interface simplies I/O system design
130 mm x 100 mm x 45 mm (height) form factor
Small-footprint, upgradeable
JTAG (IEEE 1149) boundary-scan interface
Board-level testability
System interface through two impedance-controlled
connectors
High-performance and reliable signal integrity
March 1999
相关PDF资料
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SMFR-29C516ESC 16-BIT ERROR DETECT AND CORRECT CKT, QFP100
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