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参数资料
| 型号： | SME5434PCI-480 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, XMA |
| 封装： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件页数： | 5/34页 |
| 文件大小： | 418K |
| 代理商： | SME5434PCI-480 |
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13
360/440/480MHz CPU; 0.25 to 2 MB L2 cache, UPA64S, 66MHz PCI
UltraSPARC-IIi CPU Module
March 1999
Sun Microsystems, Inc
SME5431PCI-360
SME5434PCI-440
SME5434PCI-480
Preliminary
CLOCK DISTRIBUTION
A high-frequency clock signal is generated within the module using a Motorola MC12430 high frequency PLL
clock generator from a 16MHz series resonant crystal. The clocks are differential Low Voltage Positive ECL
(LVPECL). The MC12430 provides a serial and parallel interface for setting the frequency. The parallel inter-
face pins are hardwired on the module and their state is loaded during reset. The serial interface signals
S_LOAD, S_DATA, and S_CLOCK are brought out to the Memory/UPA64S external connector to allow fre-
quency setting from the system board.
The high-frequency clock from the clock generator is divided down by a MC100LVEL39 clock divider to pro-
duce the processor and UPA64S clock signals. Only the UPA64S LV PECL clock signal (at 1/4 of the CPU clock
frequency) is a module output. It appears on the 180-pin Memory/UPA64S external connector.
An MC100LVEP210 clock buffer distributes the HSTL-level clocks to the CPU and SRAM. Figure 3 shows a
schematic diagram of the module clock distribution.
Figure 3. Module Clock Distribution
The JTAG TCLK signal enters the module via the 120-pin PCI/JTAG/Temperature Sense connector and con-
nects to the SRAMs and the UltraSPARC-IIi CPU.
PCI Clock
UPA64S
f/2
f/4
SRAM
Clock Generator
MC12430
Frequency Divider MC100LVE39
Clock Buffer
UltraSPARC-II
i
MC100LVEP210
Note 1
Note 1: The CPU’s PLL doubles the incoming frequency for the CPU pipeline
Parallel Interface
Serial Interface
Note 2: Multiple HSTL pins connect to the SRAMs
Note 2
CPU
Bus
LVPECL outputs
HSTL outputs
Module boundary
CPU_CLK
SRAM_CLK
UPA_CLK
CPU_CLK
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