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参数资料
| 型号： | SME5434PCI-480 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, XMA |
| 封装： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件页数： | 2/34页 |
| 文件大小： | 418K |
| 代理商： | SME5434PCI-480 |
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SME5431PCI-360
SME5434PCI-440
SME5434PCI-480
Preliminary
360/440/480MHz CPU; 0.25 to 2 MB L2 cache, UPA64S, 66MHz PCI
UltraSPARC-IIi CPU Module
March 1999
Sun Microsystems, Inc
PCI interface
Symbol
Type
Name and Function
PPCI_AD[31:0]
I/O
Address and data bits are multiplexed on these PCI pins
PPCI_CBE_L[3:0]
I/O
Bus command and byte enables are multiplexed on these PCI pins
PPCI_PAR
I/O
Parity: even parity generated across AD[31:0] and CBE_L[3:0]
PPCI_DEVSEL_L
STS [1]
1. Sustained tri-state, bidirectional; only one driver at a time; must drive high for one cycle before letting the line oat. External pullups
maintain the high voltage level between drives and are needed on the system board.
Device Select: indicates the driving device has decoded its address as the target of the
current access: as input, indicates whether any device has been selected
PPCI_FRAME_L
STS
Cycle Frame: driven by current master to indicate beginning and end of an access
PPCI_REQ_L[3:0]
I
Request: indicates to arbiter that an external device requires use of the bus
PPCI_GNT_L[3:0]
T/S [2]
2. Tri-state output.
Grant: indicates to device that access to the bus has been granted
PPCI_IRDY_L
STS
Initiator Ready: indicates the bus master’s ability to complete the current data phase
PPCI_TRDY_L
STS
Target Ready: indicates the selected device’s ability to complete the current data phase.
PPCI_PERR_L
O/D [3]
3. Open drain as STS, but allows multiple devices to be wire-ORd. A pullup is required to sustain the inactive state, and should be
implemented on the system board.
Parity error: reports data parity errors
PPCI_SERR_L
O/D
System Error: reports address parity errors, data parity errors on special cycles, or any
other catastrophic PCI errors
PPCI_STOP_L
STS
Stop: indicates that current target is requesting that the master stop the current
transaction
Interrupt Interface
Symbol
Type
Name and Function
SB_DRAIN
O
Store Buffer Drain; asserted after Interrupts or by software to cause outstanding DMA
writes to be ushed from buffers
SB_EMPTY[1:0]
I
Store Buffer Empty; asserted when external SIMBA PCI bus bridge has guaranteed that
all DMA writes queued before the assertion of SB_DRAIN have left the bus bridge
INT_NUM[5:0]
I
Interrupt Number; sampled at 66 MHz PCI clock rate; encoded Interrupt request
Memory and Transceivers Interface
Symbol
Type
Name and Function
MEM_WE_L
O
Memory Write Enable: active low
MEM_CAS_L[1:0]
O
Memory Column Address Strobe: active low
MEM_RAST_L[3:0]
O
Memory Row Address Strobe, Top: active low
MEM_RASB_L[3:0]
O
Memory Row Address Strobe, Bottom: active low
SYS_DAT[63:0]
I/O
Memory / UPA64S Data
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