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参数资料
| 型号： | SMJL-29C80F/883 |
| 厂商： | ATMEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 12-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, CQCC44 |
| 封装： | MQFP-44 |
| 文件页数： | 14/18页 |
| 文件大小： | 287K |
| 代理商： | SMJL-29C80F/883 |
29C80F
Rev. D (25 Mar.97)
69
MATRA MHS
Figure 4. 12 bit 2’s Complement Coefficient Format for IDCT.
* IDCT :
The input data, for IDCT, is a 12-bit 2’s complement number (coefficient) in the range –2048, 2047.
Pin
DI11
DI10
DI9
DI8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Weight
– 2048
1024
512
256
128
64
32
16
8
4
2
1
Digital value
– 211
210
29
28
27
26
25
24
23
22
21
20
DO[...] : The data output port is updated on each rising edge of CLK.
*FDCT :
The output data, for FDCT, is a 12 bit 2’s complement number (coefficient) in the range (–2048, 2047). Note that an inside clipping
is performed before outputting the data onto this range.
Figure 5. 12 bit 2’s Complement Coefficient Format for FDCT.
Pin
DO11
DO10
DO9
DO8
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Weight
– 2048
1024
512
256
128
64
32
16
8
4
2
1
Digital value
– 211
210
29
28
27
26
25
24
23
22
21
20
*IDCT :
The output data, for IDCT, is a 9 (8)-bit 2’s complement number (pixel) in the range –256, 257 (–128, 127). Note that an inside
clipping is performed before outputting the data onto this range.
Figure 6. 12 bit 2’s Complement Coefficient Format for FDCT.
Pin
DO11
DO10
DO9
DO8
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Weight
– 256
128
64
32
16
8
4
2
1
–
Digital value
– 28
27
26
25
24
23
22
21
20
(*)
(*) Forced to VOL
Figure 7.8 bit 2’s Complement Pixel Format for IDCT.
Pin
DO11
DO10
DO9
DO8
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Weight
– 128
65
32
16
8
4
2
1
–
Digital value
– 27
26
25
24
23
22
21
20
(*)
(*) Forced to VOL
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