参数资料
| 型号： | SMP18FS-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | IC AMP SAMPLE HOLD OCTAL 16SOIC |
| 标准包装： | 2,500 |
| 放大器类型： | 采样和保持 |
| 电路数： | 8 |
| 转换速率： | 7 V/µs |
| 电流 - 输入偏压： | 500nA |
| 电压 - 输入偏移： | 2500µV |
| 电流 - 电源： | 6mA |
| 电流 - 输出 / 通道： | 1.2mA |
| 电压 - 电源，单路/双路(±)： | 5 V ~ 12 V，±2.5 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Linearity Error
–3 V
≤ V
IN ≤ +3 V
0.01
%
Buffer Offset Voltage
VOS
TA = +25°C, VIN = 0 V
2.5
10
mV
–40
°C ≤ T
A ≤ +85°C, VIN = 0 V
3.5
20
mV
Hold Step
VHS
VIN = 0 V, TA = +25°C to +85°C
46mV
VIN = 0 V, TA = –40°C8
mV
Droop Rate
V
CH/tTA = +25°C, VIN = 0 V
2
40
mV/s
Output Source Current
ISOURCE
VIN = 0 V
1
1.2
mA
Output Sink Current
ISINK
VIN = 0 V
1
0.5
mA
Output Voltage Range
RL = 20 k
–3.0
+3.0
V
LOGIC CHARACTERISTICS
Logic Input High Voltage
VINH
2.4
V
Logic Input Low Voltage
VINL
0.8
V
Logic Input Current
IIN
VIN = 2.4 V
0.5
1
A
DYNAMIC PERFORMANCE
2
Acquisition Time
3
tAQ
TA = +25°C, –3 V to +3 V to 0.1%
3.5
s
Hold Mode Settling Time
tH
To
±1 mV of Final Value
1
s
Channel Select Time
tCH
90
ns
Channel Deselect Time
tDCS
45
ns
Inhibit Recovery Time
tIR
90
ns
Slew Rate
SR
6
V/
s
Capacitive Load Stability
<30% Overshoot
500
pF
Analog Crosstalk
–3 V to +3 V Step
–72
dB
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
PSRR
VSS = ± 5 V to ± 6 V
60
75
dB
Supply Current
IDD
TA = +25°C
5.5
7.5
mA
–40
°C ≤ T
A ≤ +85°C
7.5
9.5
mA
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Limits
Linearity Error
60 mV
≤ V
IN ≤ 10 V
0.01
%
Buffer Offset Voltage
VOS
TA = +25°C, VIN = 6 V
2.5
10
mV
–40
°C ≤ T
A ≤ +85°C, VIN = 6 V
3.5
20
mV
Hold Step
VHS
VIN = 6 V, TA = +25°C to +85°C
46mV
VIN = 6 V, TA = –40°C8
mV
Droop Rate
V
CH/tTA = +25°C, VIN = 6 V
2
40
mV/s
Output Source Current
ISOURCE
VIN = 6 V
1
1.2
mA
Output Sink Current
ISINK
VIN = 6 V
1
0.5
mA
Output Voltage Range
RL = 20 k
0.06
10.0
V
RL = 10 k
0.06
9.5
V
LOGIC CHARACTERISTICS
Logic Input High Voltage
VINH
2.4
V
Logic Input Low Voltage
VINL
0.8
V
Logic Input Current
IIN
VIN = 2.4 V
0.5
1
A
DYNAMIC PERFORMANCE
2
Acquisition Time
3
tAQ
TA = +25°C, 0 to 10 V to 0.1%
2.5
3.25
s
Hold Mode Settling Time
tH
To
±1 mV of Final Value
1
s
Channel Select Time
tCH
90
ns
Channel Deselect Time
tDCS
45
ns
Inhibit Recovery Time
tIR
90
ns
Slew Rate
4
SR
7
V/
s
Capacitive Load Stability
<30% Overshoot
500
pF
Analog Crosstalk
0 V to 10 V Step
–72
dB
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
PSRR
10.8 V
≤ V
DD ≤ 13.2 V
60
75
dB
Supply Current
IDD
TA = +25°C
6.0
8.0
mA
–40
°C ≤ T
A ≤ +85°C
8.0
10.0
mA
NOTES
1Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels.
2All input control signals are specified with t
r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3This parameter is guaranteed without test.
4Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%.
Specifications subject to change without notice.
REV. C
–2–
SMP18–SPECIFICATIONS
(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –40 C to +85 C for SMP18F,
unless otherwise noted)
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –40 C to +85 C for SMP18F,
unless otherwise noted)
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