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| 型号： | SN54LVTH18504AHV |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | Octal 3-State Noninverting Buffer/Line Driver/Line Receiver; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000 |
| 中文描述： | 的3.3V ABT生根粉扫描测试设备与20位通用总线收发器 |
| 文件页数： | 6/35页 |
| 文件大小： | 544K |
| 代理商： | SN54LVTH18504AHV |
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SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Std 1149.1-1990.
Test instructions, test data, and test control signals are passed along this serial-test bus. The TAP controller
monitors two signals from the test bus: TCK and TMS. The TAP controller extracts the synchronization (TCK)
and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the
test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Std 1149.1-1990 4-wire test bus and boundary-scan architecture
and the relationships of the test bus, the TAP controller, and the test registers. As shown, the device contains
an 8-bit instruction register and four test data registers: a 48-bit boundary-scan register, a 3-bit boundary-control
register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Update-DR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = L
TMS = H
TMS = L
Exit2-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-IR
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| SN54LVTH182504A | 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(20位通用总线收发器)) |
| SN54LVTH18504A | 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(20位通用总线收发器)) |
| SN54LVTH182646AHV | Octal 3-State Noninverting Buffer/Line Driver/Line Receiver; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Rail; Qty per Container: 75 |
| SN54LVTH18646AHV | Octal 3-State Noninverting Buffer/Line Driver/Line Receiver; Package: SOEIAJ-20; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2000 |
| SN54LVTH182652AHV | Octal 3-State Noninverting Buffer/Line Driver/Line Receiver; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500 |
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