参数资料
型号: SN54LVTH18652AHV
厂商: Texas Instruments, Inc.
英文描述: Octal 3-State Noninverting Buffer/Line Driver/Line Receiver; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18
中文描述: 的3.3V ABT生根粉扫描测试设备与18位收发器和寄存器
文件页数: 17/38页
文件大小: 606K
代理商: SN54LVTH18652AHV
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each
falling edge of TCK. Figures 6 and 7 illustrate the 36-bit linear-feedback shift-register algorithms through which
the patterns are generated. An initial seed value should be scanned into the BSR prior to performing this
operation. A seed value of all zeroes does not produce additional patterns.
=
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
1B9-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
1A8-I/O
1A9-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
2A8-I/O
2A9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
2B9-I/O
Figure 6. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 1)
相关PDF资料
PDF描述
SN54LVTH18512 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器))
SN54LVTH182512 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(18位通用总线收发器))
SN54LVTH18514 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(20位通用总线收发器))
SN54LVTH182514 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(20位通用总线收发器))
SN74LVTH182514 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3V ABT扫描测试装置(20位通用总线收发器))
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