- 您现在的位置：买卖IC网 > PDF目录98091 > SN74ABT18502PMR (TEXAS INSTRUMENTS INC) ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 PDF资料下载
参数资料
| 型号： | SN74ABT18502PMR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| 封装： | GREEN, PLASTIC, LQFP-64 |
| 文件页数： | 29/32页 |
| 文件大小： | 578K |
| 代理商： | SN74ABT18502PMR |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页
SN74ABT18502
SCAN TEST DEVICE
WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS753 – FEBRUARY 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram is shown in Figure 1 and is in accordance with IEEE Std 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As illustrated, the TAP controller consists of sixteen states. There are six stable states (indicated by a looping
arrow in the state diagram) and ten unstable states. A stable state is defined as a state the TAP controller can
retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths though the state diagram: one to access and control the selected DR and one to
access and control the IR. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The IR is reset to an opcode that
selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain DRs may also be reset
to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected
or if a board defect causes it to be open circuited.
For the SN74ABT18502, the IR is reset to the binary value 10000001, which selects the IDCODE instruction.
Each bit in the BSR is reset to logic 0 except bits 83–80, which are reset to logic 1. The BCR is reset to the binary
value 000000000000000000010, which selects the PSA test operation with no input masking.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state can also be entered following DR or IR scans. Run-Test/Idle is provided as
a stable state in which the test logic may be actively running a test or can be idle.
The test operations selected by the BCR are performed while the TAP controller is in the Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states are provided to allow the selection of either DR scan
or IR scan.
Capture-DR
When a DR scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR
state, the selected DR can capture a data value as specified by the current instruction. Such capture operations
occur on the rising edge of TCK upon which the TAP controller exits the Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the DR is placed in the scan path between TDI and TDO and, on the first falling
edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present
in the least significant bit (LSB) of the selected DR.
While in the stable Shift-DR state, data is serially shifted through the selected DR on each TCK cycle. The first
shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the
TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The
last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74ABT18502PM | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| SN74ABT18504PMRG4 | ABT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| SN74ABT18640DGGR | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56 |
| SN74ABT18640DLR | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56 |
| SN74ABT2240ADWRG4 | ABT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74ABT18502PMRG4 | 功能描述:特定功能逻辑 W/18-Bit Univ Bus Trncvr RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
| SN74ABT18502PN | 制造商:TI 功能描述:74ABT18502 S1A4B |
| SN74ABT18504 | 制造商:TI 制造商全称:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS |
| SN74ABT18504PM | 功能描述:特定功能逻辑 Device w/20-Bit Univ Bus Transceiver RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
| SN74ABT18504PMG4 | 功能描述:特定功能逻辑 Device w/20-Bit Univ Bus Transceiver RoHS:否 制造商:Texas Instruments 产品: 系列:SN74ABTH18502A 工作电源电压:5 V 封装 / 箱体:LQFP-64 封装:Tube |
发布紧急采购，3分钟左右您将得到回复。