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参数资料
| 型号： | SN74GTL16612ADLR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | GTL/TVC SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封装： | PLASTIC, SSOP-56 |
| 文件页数： | 2/14页 |
| 文件大小： | 234K |
| 代理商： | SN74GTL16612ADLR |
www.ti.com
APPLICATION INFORMATION
OEC
Termination Voltage, V
TT
Reference Voltage, V
REF
VREF
VTT
C
R
2R
Partial Power Down
Bus-Hold Circuit
SN54GTL16612A, SN74GTL16612A
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED JULY 2005
The 'GTL16612A GTL output consists of an improved edge-control circuit that provides optimized rise and fall
times, typically 2.6 ns (20% to 80%), for backplanes under various loading conditions.
Using the definition of slew rate
t/v = t
r or tf/(VOH – VOL), the slew rate of the device typically is 5 ns/V. As a
comparison, these values are significantly more than those of previous GTL or standard TTL devices, which are
usually about 1 ns/V, or less.
The termination voltage (VTT) should be derived from a voltage regulator that can provide up to 50-mA current
per signal line. There are various voltage regulators that meet these requirements. Depending on the application,
the regulators should be mounted either directly on the backplane or on the daughter boards. It is highly
recommended that ceramic bypass capacitors be used (due to high impedance) at the termination resistors
because several signal lines may be switching simultaneously, causing considerable current fluctuations at the
termination voltage.
The GTL reference voltage (VREF) can be derived using a simple voltage divider between VTT and GND with an
R-to-2R ratio and a bypass capacitor (0.01–0.1
F) as close to the V
REF terminal as possible (see Figure 4).
Generating VREF from VTT ensures the maximum possible signal-to-noise ratio (SNR) even with an unstable
termination voltage. It also is recommended to generate VREF locally on each plug-in card, instead of on the
backplane.
Figure 4. Suggested Connection of VREF Terminal
Device power can be switched off without having to remove the device from the system. This is a partial power
down. 'GTL16612A can be used in a partial-power-down application where VCC = 0 because the inputs and
outputs are at high impedance and are able to tolerate active bus signals. This is reflected in the Ioff parameter,
which specifies the maximum input or output leakage current.
Bus hold on A-port inputs (LVTTL side) prevents any unused or floating inputs from damaging the device. To
change the logic state stored by the bus-hold circuit, a current of about 250-300
A must be overridden. There is
no bus hold on the B port (GTL side). A bus-hold circuit on the GTL side would defeat the purpose of the
open-drain outputs, which take on the high-impedance state to allow the bus to achieve a logic high state via the
pullup resistors.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74GTL16612DGGR | 功能描述:转换 - 电压电平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| SN74GTL16612DL | 功能描述:转换 - 电压电平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| SN74GTL16612DLG4 | 功能描述:转换 - 电压电平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| SN74GTL16612DLR | 功能描述:转换 - 电压电平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| SN74GTL16612DLRG4 | 功能描述:转换 - 电压电平 3-8-Line Decoder Demltplxr RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
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