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参数资料
| 型号： | SN74HSTL16919DGGR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | TTL/H/L SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | GREEN, PLASTIC, TSSOP-48 |
| 文件页数： | 1/10页 |
| 文件大小： | 297K |
| 代理商： | SN74HSTL16919DGGR |
SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of Texas Instruments’ Widebus
Family
D Inputs Meet JEDEC HSTL Std JESD 8-6,
and Outputs Meet Level III Specifications
D 10-k Pullup Resistor on Data and LE
Inputs
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
This 9-bit to 18-bit D-type latch is designed for
3.15-V to 3.45-V VCC operation. The D inputs
accept HSTL levels and the Q outputs provide
LVTTL levels.
The SN74HSTL16919 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of nine outputs is controlled with its
own latch-enable (LE) input.
Each of the nine D inputs is tied to the inputs of two
D-type latches that provide true data (Q) at the
outputs. While LE is low, the Q outputs of the
corresponding nine latches follow the D inputs.
When LE is taken high, the Q outputs are latched
at the levels set up at the D inputs.
To ensure low ICC during power up or power down, 10-k pullup resistors are included on the D and LE inputs
to ensure a differential voltage relative to VREF. VREF must be applied prior to or at the same time as VCC, or
VREF must be pulled down to ground.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0
°C to 70°C
TSSOP – DGG
Tape and reel
SN74HSTL16919DGGR
HSTL16919
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
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7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
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45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2Q1
1Q1
GND
D1
D2
VCC
D3
D4
GND
1LE
GND
VREF
GND
2LE
GND
D5
D6
D7
VCC
D8
D9
GND
2Q9
1Q9
VCC
1Q2
2Q2
GND
1Q3
2Q3
VCC
1Q4
2Q4
GND
1Q5
2Q5
GND
1Q6
2Q6
VCC
1Q7
2Q7
GND
1Q8
2Q8
VCC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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