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参数资料
| 型号： | SN74HSTL16919DGGR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | TTL/H/L SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | GREEN, PLASTIC, TSSOP-48 |
| 文件页数： | 6/10页 |
| 文件大小： | 297K |
| 代理商： | SN74HSTL16919DGGR |
SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
LOAD CIRCUIT
Data Input
VREF
1.25 V
0.25 V
VREF
1.25 V
0.25 V
1.25 V
0.25 V
VREF
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
VREF
1.25 V
0.25 V
VOH
VOL
Input
(see Note B)
Output
VREF
From Output
Under Test
CL = 80 pF
(see Note A)
500
LE
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 1 ns, tf ≤ 1 ns.
C. The outputs are measured one at a time with one transition per measurement.
D. tPHL and tPLH are the same as tpd.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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