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参数资料
| 型号： | SN74HSTL16919DGGR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | TTL/H/L SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | GREEN, PLASTIC, TSSOP-48 |
| 文件页数： | 4/10页 |
| 文件大小： | 297K |
| 代理商： | SN74HSTL16919DGGR |
SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3.15
3.45
V
VREF
Reference voltage
0.68
0.75
0.9
V
VI
Input voltage
0
1.5
V
VIH
AC high-level input voltage
All inputs
VREF+200 mV
V
VIL
AC low-level input voltage
All inputs
VREF–200 mV
V
VIH
DC high-level input voltage
All inputs
VREF+100 mV
V
VIL
DC low-level input voltage
All inputs
VREF–100 mV
V
IOH
High-level output current
–24
mA
IOL
Low-level output current
24
mA
TA
Operating free-air temperature
0
70
°C
NOTE 3: All unused inputs of the device must maintain a minimum differential voltage of 100 mV between data inputs and VREF to ensure proper
device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 3.15 V,
II = –18 mA
–1.2
V
VOH
VCC = 3.15 V,
IOH = –24 mA
2.4
V
VOL
VCC = 3.15 V,
IOL = 24 mA
0.5
V
Control inputs
VI = 0 or 1.5 V
–500
II
Data inputs
VCC = 3.45 V
VI = 0 or 1.5 V
–500
A
VREF
VREF = 0.68 V or 0.9 V
90
ICC
VCC = 3.45 V,
VI = 0 or 1.5 V
50
100
mA
Ci
Control inputs
VCC = 0 or 3.3 V,
VI = 0 or 3.3 V
2.5
pF
Ci
Data inputs
VCC = 0 or 3.3 V,
VI = 0 or 3.3 V
2.5
pF
Co
Outputs
VCC = 0,
VO = 0
2.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.15 V
UNIT
MIN
MAX
tw
Pulse duration, LE low
3
ns
tsu
Setup time, D before LE
↑
2
ns
th
Hold time
D after LE
↑
1
ns
tldr
Data race condition time
D after LE
↓
0
ns
This is the maximum time after LE switches low that the data input can return to the latched state from the opposite state without producing a
glitch on the output.
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